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a5d23e3aee
Sync patch with upstream version and tag them. Minor changes done to Pinctrl patch to support older kernel. Patch automatically refreshed with make target/linux/refresh. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
153 lines
3.9 KiB
Diff
153 lines
3.9 KiB
Diff
From f98eded9e9ab048c88ff59c5523e703a6ced5523 Mon Sep 17 00:00:00 2001
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From: Lorenzo Bianconi <lorenzo@kernel.org>
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Date: Tue, 12 Nov 2024 01:08:52 +0100
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Subject: [PATCH 4/6] clk: en7523: fix estimation of fixed rate for EN7581
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Introduce en7581_base_clks array in order to define per-SoC fixed-rate
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clock parameters and fix wrong parameters for emi, npu and crypto EN7581
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clocks
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Fixes: 66bc47326ce2 ("clk: en7523: Add EN7581 support")
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Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
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Link: https://lore.kernel.org/r/20241112-clk-en7581-syscon-v2-5-8ada5e394ae4@kernel.org
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Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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---
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drivers/clk/clk-en7523.c | 105 ++++++++++++++++++++++++++++++++++++++-
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1 file changed, 103 insertions(+), 2 deletions(-)
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--- a/drivers/clk/clk-en7523.c
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+++ b/drivers/clk/clk-en7523.c
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@@ -37,6 +37,7 @@
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#define REG_NP_SCU_SSTR 0x9c
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#define REG_PCIE_XSI0_SEL_MASK GENMASK(14, 13)
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#define REG_PCIE_XSI1_SEL_MASK GENMASK(12, 11)
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+#define REG_CRYPTO_CLKSRC2 0x20c
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#define REG_RST_CTRL2 0x00
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#define REG_RST_CTRL1 0x04
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@@ -89,6 +90,10 @@ static const u32 emi_base[] = { 33300000
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static const u32 bus_base[] = { 500000000, 540000000 };
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static const u32 slic_base[] = { 100000000, 3125000 };
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static const u32 npu_base[] = { 333000000, 400000000, 500000000 };
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+/* EN7581 */
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+static const u32 emi7581_base[] = { 540000000, 480000000, 400000000, 300000000 };
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+static const u32 npu7581_base[] = { 800000000, 750000000, 720000000, 600000000 };
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+static const u32 crypto_base[] = { 540000000, 480000000 };
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static const struct en_clk_desc en7523_base_clks[] = {
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{
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@@ -186,6 +191,102 @@ static const struct en_clk_desc en7523_b
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}
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};
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+static const struct en_clk_desc en7581_base_clks[] = {
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+ {
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+ .id = EN7523_CLK_GSW,
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+ .name = "gsw",
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+
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+ .base_reg = REG_GSW_CLK_DIV_SEL,
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+ .base_bits = 1,
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+ .base_shift = 8,
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+ .base_values = gsw_base,
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+ .n_base_values = ARRAY_SIZE(gsw_base),
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+
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+ .div_bits = 3,
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+ .div_shift = 0,
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+ .div_step = 1,
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+ .div_offset = 1,
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+ }, {
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+ .id = EN7523_CLK_EMI,
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+ .name = "emi",
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+
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+ .base_reg = REG_EMI_CLK_DIV_SEL,
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+ .base_bits = 2,
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+ .base_shift = 8,
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+ .base_values = emi7581_base,
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+ .n_base_values = ARRAY_SIZE(emi7581_base),
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+
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+ .div_bits = 3,
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+ .div_shift = 0,
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+ .div_step = 1,
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+ .div_offset = 1,
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+ }, {
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+ .id = EN7523_CLK_BUS,
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+ .name = "bus",
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+
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+ .base_reg = REG_BUS_CLK_DIV_SEL,
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+ .base_bits = 1,
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+ .base_shift = 8,
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+ .base_values = bus_base,
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+ .n_base_values = ARRAY_SIZE(bus_base),
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+
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+ .div_bits = 3,
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+ .div_shift = 0,
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+ .div_step = 1,
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+ .div_offset = 1,
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+ }, {
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+ .id = EN7523_CLK_SLIC,
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+ .name = "slic",
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+
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+ .base_reg = REG_SPI_CLK_FREQ_SEL,
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+ .base_bits = 1,
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+ .base_shift = 0,
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+ .base_values = slic_base,
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+ .n_base_values = ARRAY_SIZE(slic_base),
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+
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+ .div_reg = REG_SPI_CLK_DIV_SEL,
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+ .div_bits = 5,
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+ .div_shift = 24,
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+ .div_val0 = 20,
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+ .div_step = 2,
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+ }, {
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+ .id = EN7523_CLK_SPI,
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+ .name = "spi",
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+
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+ .base_reg = REG_SPI_CLK_DIV_SEL,
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+
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+ .base_value = 400000000,
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+
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+ .div_bits = 5,
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+ .div_shift = 8,
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+ .div_val0 = 40,
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+ .div_step = 2,
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+ }, {
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+ .id = EN7523_CLK_NPU,
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+ .name = "npu",
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+
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+ .base_reg = REG_NPU_CLK_DIV_SEL,
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+ .base_bits = 2,
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+ .base_shift = 8,
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+ .base_values = npu7581_base,
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+ .n_base_values = ARRAY_SIZE(npu7581_base),
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+
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+ .div_bits = 3,
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+ .div_shift = 0,
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+ .div_step = 1,
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+ .div_offset = 1,
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+ }, {
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+ .id = EN7523_CLK_CRYPTO,
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+ .name = "crypto",
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+
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+ .base_reg = REG_CRYPTO_CLKSRC2,
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+ .base_bits = 1,
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+ .base_shift = 0,
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+ .base_values = crypto_base,
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+ .n_base_values = ARRAY_SIZE(crypto_base),
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+ }
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+};
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+
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static const u16 en7581_rst_ofs[] = {
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REG_RST_CTRL2,
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REG_RST_CTRL1,
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@@ -457,8 +558,8 @@ static void en7581_register_clocks(struc
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u32 rate;
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int i;
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- for (i = 0; i < ARRAY_SIZE(en7523_base_clks); i++) {
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- const struct en_clk_desc *desc = &en7523_base_clks[i];
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+ for (i = 0; i < ARRAY_SIZE(en7581_base_clks); i++) {
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+ const struct en_clk_desc *desc = &en7581_base_clks[i];
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u32 val, reg = desc->div_reg ? desc->div_reg : desc->base_reg;
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int err;
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