mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-22 15:02:32 +00:00
961b8efb5b
In case a PCI device is physical present, the Lantiq PCI driver need to
be loaded prior to the Lantiq PCIe driver. Otherwise none of them will
work because updating the BAR 0 of a device attached to the PCIe Bus
will fail.
Till kernel commit 9667bb039bf6 ("MIPS: lantiq: remove unnecessary
of_platform_default_populate call"), the Lantiq PCI driver was probed
early in the boot process via plat_of_setup().
Since the mentioned commit, both drivers are probed via
of_platform_default_populate_init() and they are probed according to
their order in the devicetree source file.
If the Lantiq PCI driver is enabled in the devicetree, defer the probing
og the Lantiq PCIe driver till the Lantiq PCI driver is probed. Use the
presence of a PCU bus as indicater for a loaded Lantiq PCI driver.
This way we don't need to shuffle the PCI/PCIe nodes in the devicetree
source file, as they are already (correctly) ordered based on the unit
address.
Signed-off-by: Mathias Kresin <dev@kresin.me>
192 lines
5.6 KiB
Diff
192 lines
5.6 KiB
Diff
--- a/arch/mips/pci/ifxmips_pcie.c
|
|
+++ b/arch/mips/pci/ifxmips_pcie.c
|
|
@@ -18,6 +18,9 @@
|
|
#include <linux/pci_regs.h>
|
|
#include <linux/module.h>
|
|
|
|
+#include <linux/of_gpio.h>
|
|
+#include <linux/of_platform.h>
|
|
+
|
|
#include "ifxmips_pcie.h"
|
|
#include "ifxmips_pcie_reg.h"
|
|
|
|
@@ -40,6 +43,7 @@
|
|
static DEFINE_SPINLOCK(ifx_pcie_lock);
|
|
|
|
u32 g_pcie_debug_flag = PCIE_MSG_ANY & (~PCIE_MSG_CFG);
|
|
+static int pcie_reset_gpio;
|
|
|
|
static ifx_pcie_irq_t pcie_irqs[IFX_PCIE_CORE_NR] = {
|
|
{
|
|
@@ -82,6 +86,22 @@ void ifx_pcie_debug(const char *fmt, ...
|
|
printk("%s", buf);
|
|
}
|
|
|
|
+static inline void pcie_ep_gpio_rst_init(int pcie_port)
|
|
+{
|
|
+ gpio_direction_output(pcie_reset_gpio, 1);
|
|
+ gpio_set_value(pcie_reset_gpio, 1);
|
|
+}
|
|
+
|
|
+static inline void pcie_device_rst_assert(int pcie_port)
|
|
+{
|
|
+ gpio_set_value(pcie_reset_gpio, 0);
|
|
+}
|
|
+
|
|
+static inline void pcie_device_rst_deassert(int pcie_port)
|
|
+{
|
|
+ mdelay(100);
|
|
+ gpio_direction_output(pcie_reset_gpio, 1);
|
|
+}
|
|
|
|
static inline int pcie_ltssm_enable(int pcie_port)
|
|
{
|
|
@@ -1045,17 +1065,52 @@ pcie_rc_initialize(int pcie_port)
|
|
return 0;
|
|
}
|
|
|
|
-static int __init ifx_pcie_bios_init(void)
|
|
+static int ifx_pcie_bios_probe(struct platform_device *pdev)
|
|
{
|
|
+ struct device_node *node = pdev->dev.of_node;
|
|
void __iomem *io_map_base;
|
|
int pcie_port;
|
|
int startup_port;
|
|
|
|
+ struct device_node *np;
|
|
+ struct pci_bus *bus;
|
|
+
|
|
+ /*
|
|
+ * In case a PCI device is physical present, the Lantiq PCI driver need
|
|
+ * to be loaded prior to the Lantiq PCIe driver. Otherwise none of them
|
|
+ * will work.
|
|
+ *
|
|
+ * In case the lantiq PCI driver is enabled in the device tree, check if
|
|
+ * a PCI bus (hopefully the one of the Lantiq PCI driver one) is already
|
|
+ * registered.
|
|
+ *
|
|
+ * It will fail if there is another PCI controller, this controller is
|
|
+ * registered before the Lantiq PCIe driver is probe and the lantiq PCI
|
|
+ */
|
|
+ np = of_find_compatible_node(NULL, NULL, "lantiq,pci-xway");
|
|
+
|
|
+ if (of_device_is_available(np)) {
|
|
+ bus = pci_find_next_bus(bus);
|
|
+
|
|
+ if (!bus)
|
|
+ return -EPROBE_DEFER;
|
|
+ }
|
|
+
|
|
/* Enable AHB Master/ Slave */
|
|
pcie_ahb_pmu_setup();
|
|
|
|
startup_port = IFX_PCIE_PORT0;
|
|
-
|
|
+
|
|
+ pcie_reset_gpio = of_get_named_gpio(node, "gpio-reset", 0);
|
|
+ if (gpio_is_valid(pcie_reset_gpio)) {
|
|
+ int ret = devm_gpio_request(&pdev->dev, pcie_reset_gpio, "pcie-reset");
|
|
+ if (ret) {
|
|
+ dev_err(&pdev->dev, "failed to request gpio %d\n", pcie_reset_gpio);
|
|
+ return ret;
|
|
+ }
|
|
+ gpio_direction_output(pcie_reset_gpio, 1);
|
|
+ }
|
|
+
|
|
for (pcie_port = startup_port; pcie_port < IFX_PCIE_CORE_NR; pcie_port++){
|
|
if (pcie_rc_initialize(pcie_port) == 0) {
|
|
IFX_PCIE_PRINT(PCIE_MSG_INIT, "%s: ifx_pcie_cfg_base 0x%p\n",
|
|
@@ -1067,6 +1122,7 @@ static int __init ifx_pcie_bios_init(voi
|
|
return -ENOMEM;
|
|
}
|
|
ifx_pcie_controller[pcie_port].pcic.io_map_base = (unsigned long)io_map_base;
|
|
+ pci_load_of_ranges(&ifx_pcie_controller[pcie_port].pcic, node);
|
|
|
|
register_pci_controller(&ifx_pcie_controller[pcie_port].pcic);
|
|
/* XXX, clear error status */
|
|
@@ -1083,6 +1139,30 @@ static int __init ifx_pcie_bios_init(voi
|
|
|
|
return 0;
|
|
}
|
|
+
|
|
+static const struct of_device_id ifxmips_pcie_match[] = {
|
|
+ { .compatible = "lantiq,pcie-xrx200" },
|
|
+ {},
|
|
+};
|
|
+MODULE_DEVICE_TABLE(of, ifxmips_pcie_match);
|
|
+
|
|
+static struct platform_driver ltq_pci_driver = {
|
|
+ .probe = ifx_pcie_bios_probe,
|
|
+ .driver = {
|
|
+ .name = "pcie-xrx200",
|
|
+ .owner = THIS_MODULE,
|
|
+ .of_match_table = ifxmips_pcie_match,
|
|
+ },
|
|
+};
|
|
+
|
|
+int __init ifx_pcie_bios_init(void)
|
|
+{
|
|
+ int ret = platform_driver_register(<q_pci_driver);
|
|
+ if (ret)
|
|
+ pr_info("pcie-xrx200: Error registering platform driver!");
|
|
+ return ret;
|
|
+}
|
|
+
|
|
arch_initcall(ifx_pcie_bios_init);
|
|
|
|
MODULE_LICENSE("GPL");
|
|
--- a/arch/mips/pci/ifxmips_pcie_vr9.h
|
|
+++ b/arch/mips/pci/ifxmips_pcie_vr9.h
|
|
@@ -22,8 +22,6 @@
|
|
#include <linux/gpio.h>
|
|
#include <lantiq_soc.h>
|
|
|
|
-#define IFX_PCIE_GPIO_RESET 494
|
|
-
|
|
#define IFX_REG_R32 ltq_r32
|
|
#define IFX_REG_W32 ltq_w32
|
|
#define CONFIG_IFX_PCIE_HW_SWAP
|
|
@@ -53,21 +51,6 @@
|
|
#define OUT ((volatile u32*)(IFX_GPIO + 0x0070))
|
|
|
|
|
|
-static inline void pcie_ep_gpio_rst_init(int pcie_port)
|
|
-{
|
|
-
|
|
- gpio_request(IFX_PCIE_GPIO_RESET, "pcie-reset");
|
|
- gpio_direction_output(IFX_PCIE_GPIO_RESET, 1);
|
|
- gpio_set_value(IFX_PCIE_GPIO_RESET, 1);
|
|
-
|
|
-/* ifx_gpio_pin_reserve(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);
|
|
- ifx_gpio_output_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);
|
|
- ifx_gpio_dir_out_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);
|
|
- ifx_gpio_altsel0_clear(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);
|
|
- ifx_gpio_altsel1_clear(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);
|
|
- ifx_gpio_open_drain_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);*/
|
|
-}
|
|
-
|
|
static inline void pcie_ahb_pmu_setup(void)
|
|
{
|
|
/* Enable AHB bus master/slave */
|
|
@@ -180,20 +163,6 @@ static inline void pcie_phy_rst_deassert
|
|
IFX_REG_W32(reg, IFX_RCU_RST_REQ);
|
|
}
|
|
|
|
-static inline void pcie_device_rst_assert(int pcie_port)
|
|
-{
|
|
- gpio_set_value(IFX_PCIE_GPIO_RESET, 0);
|
|
-// ifx_gpio_output_clear(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);
|
|
-}
|
|
-
|
|
-static inline void pcie_device_rst_deassert(int pcie_port)
|
|
-{
|
|
- mdelay(100);
|
|
- gpio_direction_output(IFX_PCIE_GPIO_RESET, 1);
|
|
-// gpio_set_value(IFX_PCIE_GPIO_RESET, 1);
|
|
- //ifx_gpio_output_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);
|
|
-}
|
|
-
|
|
static inline void pcie_core_pmu_setup(int pcie_port)
|
|
{
|
|
struct clk *clk;
|