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238 lines
9.1 KiB
Diff
238 lines
9.1 KiB
Diff
From 4af3eff3ca4b361018749b00b71426fa23cc58a4 Mon Sep 17 00:00:00 2001
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From: Martin Sperl <kernel@martin.sperl.org>
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Date: Mon, 29 Feb 2016 12:51:41 +0000
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Subject: [PATCH 261/381] clk: bcm2835: remove use of BCM2835_CLOCK_COUNT in
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driver
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As the use of BCM2835_CLOCK_COUNT in
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include/dt-bindings/clock/bcm2835.h is frowned upon as
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it needs to get modified every time a new clock gets introduced
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this patch changes the clk-bcm2835 driver to use a different
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scheme for registration of clocks and pll, so that there
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is no more need for BCM2835_CLOCK_COUNT to be defined.
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Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
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Signed-off-by: Eric Anholt <eric@anholt.net>
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Reviewed-by: Eric Anholt <eric@anholt.net>
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(cherry picked from commit 56eb3a2ed9726961e1bcfa69d4a3f86d68f0eb52)
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---
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drivers/clk/bcm/clk-bcm2835.c | 167 ++++++++++++++++++++----------------
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include/dt-bindings/clock/bcm2835.h | 2 -
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2 files changed, 94 insertions(+), 75 deletions(-)
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--- a/drivers/clk/bcm/clk-bcm2835.c
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+++ b/drivers/clk/bcm/clk-bcm2835.c
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@@ -301,7 +301,7 @@ struct bcm2835_cprman {
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const char *osc_name;
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struct clk_onecell_data onecell;
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- struct clk *clks[BCM2835_CLOCK_COUNT];
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+ struct clk *clks[];
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};
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static inline void cprman_write(struct bcm2835_cprman *cprman, u32 reg, u32 val)
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@@ -853,6 +853,25 @@ static const struct bcm2835_clock_data b
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.is_mash_clock = true,
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};
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+struct bcm2835_gate_data {
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+ const char *name;
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+ const char *parent;
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+
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+ u32 ctl_reg;
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+};
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+
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+/*
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+ * CM_PERIICTL (and CM_PERIACTL, CM_SYSCTL and CM_VPUCTL if
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+ * you have the debug bit set in the power manager, which we
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+ * don't bother exposing) are individual gates off of the
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+ * non-stop vpu clock.
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+ */
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+static const struct bcm2835_gate_data bcm2835_clock_peri_image_data = {
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+ .name = "peri_image",
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+ .parent = "vpu",
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+ .ctl_reg = CM_PERIICTL,
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+};
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+
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struct bcm2835_pll {
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struct clk_hw hw;
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struct bcm2835_cprman *cprman;
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@@ -1658,14 +1677,81 @@ static struct clk *bcm2835_register_cloc
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return devm_clk_register(cprman->dev, &clock->hw);
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}
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+static struct clk *bcm2835_register_gate(struct bcm2835_cprman *cprman,
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+ const struct bcm2835_gate_data *data)
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+{
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+ return clk_register_gate(cprman->dev, data->name, data->parent,
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+ CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE,
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+ cprman->regs + data->ctl_reg,
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+ CM_GATE_BIT, 0, &cprman->regs_lock);
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+}
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+
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+typedef struct clk *(*bcm2835_clk_register)(struct bcm2835_cprman *cprman,
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+ const void *data);
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+struct bcm2835_clk_desc {
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+ bcm2835_clk_register clk_register;
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+ const void *data;
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+};
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+
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+#define _REGISTER(f, d) { .clk_register = (bcm2835_clk_register)f, \
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+ .data = d }
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+#define REGISTER_PLL(d) _REGISTER(&bcm2835_register_pll, d)
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+#define REGISTER_PLL_DIV(d) _REGISTER(&bcm2835_register_pll_divider, d)
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+#define REGISTER_CLK(d) _REGISTER(&bcm2835_register_clock, d)
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+#define REGISTER_GATE(d) _REGISTER(&bcm2835_register_gate, d)
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+
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+static const struct bcm2835_clk_desc clk_desc_array[] = {
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+ /* register PLL */
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+ [BCM2835_PLLA] = REGISTER_PLL(&bcm2835_plla_data),
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+ [BCM2835_PLLB] = REGISTER_PLL(&bcm2835_pllb_data),
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+ [BCM2835_PLLC] = REGISTER_PLL(&bcm2835_pllc_data),
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+ [BCM2835_PLLD] = REGISTER_PLL(&bcm2835_plld_data),
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+ [BCM2835_PLLH] = REGISTER_PLL(&bcm2835_pllh_data),
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+ /* the PLL dividers */
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+ [BCM2835_PLLA_CORE] = REGISTER_PLL_DIV(&bcm2835_plla_core_data),
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+ [BCM2835_PLLA_PER] = REGISTER_PLL_DIV(&bcm2835_plla_per_data),
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+ [BCM2835_PLLC_CORE0] = REGISTER_PLL_DIV(&bcm2835_pllc_core0_data),
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+ [BCM2835_PLLC_CORE1] = REGISTER_PLL_DIV(&bcm2835_pllc_core1_data),
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+ [BCM2835_PLLC_CORE2] = REGISTER_PLL_DIV(&bcm2835_pllc_core2_data),
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+ [BCM2835_PLLC_PER] = REGISTER_PLL_DIV(&bcm2835_pllc_per_data),
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+ [BCM2835_PLLD_CORE] = REGISTER_PLL_DIV(&bcm2835_plld_core_data),
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+ [BCM2835_PLLD_PER] = REGISTER_PLL_DIV(&bcm2835_plld_per_data),
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+ [BCM2835_PLLH_RCAL] = REGISTER_PLL_DIV(&bcm2835_pllh_rcal_data),
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+ [BCM2835_PLLH_AUX] = REGISTER_PLL_DIV(&bcm2835_pllh_aux_data),
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+ [BCM2835_PLLH_PIX] = REGISTER_PLL_DIV(&bcm2835_pllh_pix_data),
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+ /* the clocks */
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+ [BCM2835_CLOCK_TIMER] = REGISTER_CLK(&bcm2835_clock_timer_data),
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+ [BCM2835_CLOCK_OTP] = REGISTER_CLK(&bcm2835_clock_otp_data),
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+ [BCM2835_CLOCK_TSENS] = REGISTER_CLK(&bcm2835_clock_tsens_data),
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+ [BCM2835_CLOCK_VPU] = REGISTER_CLK(&bcm2835_clock_vpu_data),
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+ [BCM2835_CLOCK_V3D] = REGISTER_CLK(&bcm2835_clock_v3d_data),
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+ [BCM2835_CLOCK_ISP] = REGISTER_CLK(&bcm2835_clock_isp_data),
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+ [BCM2835_CLOCK_H264] = REGISTER_CLK(&bcm2835_clock_h264_data),
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+ [BCM2835_CLOCK_V3D] = REGISTER_CLK(&bcm2835_clock_v3d_data),
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+ [BCM2835_CLOCK_SDRAM] = REGISTER_CLK(&bcm2835_clock_sdram_data),
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+ [BCM2835_CLOCK_UART] = REGISTER_CLK(&bcm2835_clock_uart_data),
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+ [BCM2835_CLOCK_VEC] = REGISTER_CLK(&bcm2835_clock_vec_data),
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+ [BCM2835_CLOCK_HSM] = REGISTER_CLK(&bcm2835_clock_hsm_data),
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+ [BCM2835_CLOCK_EMMC] = REGISTER_CLK(&bcm2835_clock_emmc_data),
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+ [BCM2835_CLOCK_PWM] = REGISTER_CLK(&bcm2835_clock_pwm_data),
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+ /* the gates */
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+ [BCM2835_CLOCK_PERI_IMAGE] = REGISTER_GATE(
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+ &bcm2835_clock_peri_image_data),
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+};
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+
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static int bcm2835_clk_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct clk **clks;
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struct bcm2835_cprman *cprman;
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struct resource *res;
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+ const struct bcm2835_clk_desc *desc;
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+ const size_t asize = ARRAY_SIZE(clk_desc_array);
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+ size_t i;
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- cprman = devm_kzalloc(dev, sizeof(*cprman), GFP_KERNEL);
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+ cprman = devm_kzalloc(dev,
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+ sizeof(*cprman) + asize * sizeof(*clks),
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+ GFP_KERNEL);
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if (!cprman)
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return -ENOMEM;
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@@ -1682,80 +1768,15 @@ static int bcm2835_clk_probe(struct plat
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platform_set_drvdata(pdev, cprman);
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- cprman->onecell.clk_num = BCM2835_CLOCK_COUNT;
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+ cprman->onecell.clk_num = asize;
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cprman->onecell.clks = cprman->clks;
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clks = cprman->clks;
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- clks[BCM2835_PLLA] = bcm2835_register_pll(cprman, &bcm2835_plla_data);
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- clks[BCM2835_PLLB] = bcm2835_register_pll(cprman, &bcm2835_pllb_data);
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- clks[BCM2835_PLLC] = bcm2835_register_pll(cprman, &bcm2835_pllc_data);
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- clks[BCM2835_PLLD] = bcm2835_register_pll(cprman, &bcm2835_plld_data);
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- clks[BCM2835_PLLH] = bcm2835_register_pll(cprman, &bcm2835_pllh_data);
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-
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- clks[BCM2835_PLLA_CORE] =
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- bcm2835_register_pll_divider(cprman, &bcm2835_plla_core_data);
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- clks[BCM2835_PLLA_PER] =
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- bcm2835_register_pll_divider(cprman, &bcm2835_plla_per_data);
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- clks[BCM2835_PLLC_CORE0] =
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- bcm2835_register_pll_divider(cprman, &bcm2835_pllc_core0_data);
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- clks[BCM2835_PLLC_CORE1] =
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- bcm2835_register_pll_divider(cprman, &bcm2835_pllc_core1_data);
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- clks[BCM2835_PLLC_CORE2] =
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- bcm2835_register_pll_divider(cprman, &bcm2835_pllc_core2_data);
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- clks[BCM2835_PLLC_PER] =
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- bcm2835_register_pll_divider(cprman, &bcm2835_pllc_per_data);
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- clks[BCM2835_PLLD_CORE] =
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- bcm2835_register_pll_divider(cprman, &bcm2835_plld_core_data);
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- clks[BCM2835_PLLD_PER] =
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- bcm2835_register_pll_divider(cprman, &bcm2835_plld_per_data);
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- clks[BCM2835_PLLH_RCAL] =
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- bcm2835_register_pll_divider(cprman, &bcm2835_pllh_rcal_data);
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- clks[BCM2835_PLLH_AUX] =
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- bcm2835_register_pll_divider(cprman, &bcm2835_pllh_aux_data);
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- clks[BCM2835_PLLH_PIX] =
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- bcm2835_register_pll_divider(cprman, &bcm2835_pllh_pix_data);
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-
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- clks[BCM2835_CLOCK_TIMER] =
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- bcm2835_register_clock(cprman, &bcm2835_clock_timer_data);
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- clks[BCM2835_CLOCK_OTP] =
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- bcm2835_register_clock(cprman, &bcm2835_clock_otp_data);
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- clks[BCM2835_CLOCK_TSENS] =
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- bcm2835_register_clock(cprman, &bcm2835_clock_tsens_data);
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- clks[BCM2835_CLOCK_VPU] =
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- bcm2835_register_clock(cprman, &bcm2835_clock_vpu_data);
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- clks[BCM2835_CLOCK_V3D] =
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- bcm2835_register_clock(cprman, &bcm2835_clock_v3d_data);
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- clks[BCM2835_CLOCK_ISP] =
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- bcm2835_register_clock(cprman, &bcm2835_clock_isp_data);
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- clks[BCM2835_CLOCK_H264] =
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- bcm2835_register_clock(cprman, &bcm2835_clock_h264_data);
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- clks[BCM2835_CLOCK_V3D] =
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- bcm2835_register_clock(cprman, &bcm2835_clock_v3d_data);
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- clks[BCM2835_CLOCK_SDRAM] =
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- bcm2835_register_clock(cprman, &bcm2835_clock_sdram_data);
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- clks[BCM2835_CLOCK_UART] =
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- bcm2835_register_clock(cprman, &bcm2835_clock_uart_data);
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- clks[BCM2835_CLOCK_VEC] =
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- bcm2835_register_clock(cprman, &bcm2835_clock_vec_data);
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- clks[BCM2835_CLOCK_HSM] =
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- bcm2835_register_clock(cprman, &bcm2835_clock_hsm_data);
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- clks[BCM2835_CLOCK_EMMC] =
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- bcm2835_register_clock(cprman, &bcm2835_clock_emmc_data);
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-
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- /*
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- * CM_PERIICTL (and CM_PERIACTL, CM_SYSCTL and CM_VPUCTL if
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- * you have the debug bit set in the power manager, which we
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- * don't bother exposing) are individual gates off of the
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- * non-stop vpu clock.
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- */
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- clks[BCM2835_CLOCK_PERI_IMAGE] =
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- clk_register_gate(dev, "peri_image", "vpu",
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- CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE,
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- cprman->regs + CM_PERIICTL, CM_GATE_BIT,
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- 0, &cprman->regs_lock);
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-
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- clks[BCM2835_CLOCK_PWM] =
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- bcm2835_register_clock(cprman, &bcm2835_clock_pwm_data);
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+ for (i = 0; i < asize; i++) {
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+ desc = &clk_desc_array[i];
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+ if (desc->clk_register && desc->data)
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+ clks[i] = desc->clk_register(cprman, desc->data);
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+ }
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return of_clk_add_provider(dev->of_node, of_clk_src_onecell_get,
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&cprman->onecell);
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--- a/include/dt-bindings/clock/bcm2835.h
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+++ b/include/dt-bindings/clock/bcm2835.h
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@@ -44,5 +44,3 @@
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#define BCM2835_CLOCK_EMMC 28
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#define BCM2835_CLOCK_PERI_IMAGE 29
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#define BCM2835_CLOCK_PWM 30
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-
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-#define BCM2835_CLOCK_COUNT 31
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