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78858e5d6c
In the past few years, we have received several reports about SPI Flash not working properly. This is caused by excessively fast clock frequency. It's really annoying to fix them one by one. Let's reduce these aggressive frequencies to 50 MHz. This is a safe and suggested value in the vendor SDK. Signed-off-by: Shiji Yang <yangshiji66@qq.com> (cherry picked from commit 73eeac49be566d389df728b5335f7146d03d2f90) Link: https://github.com/openwrt/openwrt/pull/15919 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
121 lines
1.9 KiB
Plaintext
121 lines
1.9 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later
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#include "rt5350.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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/ {
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compatible = "zyxel,keenetic-lite-b", "ralink,rt5350-soc";
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model = "ZyXEL Keenetic Lite Rev.B";
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aliases {
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led-boot = &led_power;
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led-failsafe = &led_power;
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led-running = &led_power;
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led-upgrade = &led_power;
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};
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leds {
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compatible = "gpio-leds";
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led_power: power {
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label = "green:power";
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gpios = <&gpio0 9 GPIO_ACTIVE_LOW>;
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};
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wps {
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label = "green:wps";
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gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
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};
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};
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keys {
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compatible = "gpio-keys";
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wps {
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label = "wps";
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gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_WPS_BUTTON>;
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};
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reset {
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label = "reset";
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gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_RESTART>;
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};
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};
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};
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&spi0 {
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status = "okay";
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flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <50000000>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "u-boot";
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reg = <0x0 0x30000>;
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read-only;
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};
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partition@30000 {
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label = "u-boot-env";
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reg = <0x30000 0x10000>;
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read-only;
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};
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factory: partition@40000 {
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label = "factory";
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reg = <0x40000 0x10000>;
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read-only;
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};
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partition@50000 {
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compatible = "denx,uimage";
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label = "firmware";
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reg = <0x50000 0x7b0000>;
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};
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};
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};
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};
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&state_default {
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gpio {
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groups = "uartf";
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function = "gpio";
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};
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};
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ðernet {
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nvmem-cells = <&macaddr_factory_28>;
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nvmem-cell-names = "mac-address";
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};
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&esw {
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mediatek,portmap = <0x2f>;
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mediatek,led_polarity = <0x17>;
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};
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&wmac {
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ralink,led-polarity = <1>;
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ralink,mtd-eeprom = <&factory 0x0>;
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};
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&factory {
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compatible = "nvmem-cells";
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#address-cells = <1>;
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#size-cells = <1>;
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macaddr_factory_28: macaddr@28 {
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reg = <0x28 0x6>;
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};
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};
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