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Replace previous patch adding paths and SerDes modes with patch series pending upstream adding dedicated drivers for XFI T-PHY and USXGMII PCS, extends LynxI PCS to be a standalone platform driver and as a consequence makes much less changes to the actual Ethernet driver mtk_eth_soc. Signed-off-by: Daniel Golle <daniel@makrotopia.org>
137 lines
3.8 KiB
Diff
137 lines
3.8 KiB
Diff
From patchwork Thu Feb 1 21:52:20 2024
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Content-Type: text/plain; charset="utf-8"
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MIME-Version: 1.0
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Content-Transfer-Encoding: 7bit
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X-Patchwork-Submitter: Daniel Golle <daniel@makrotopia.org>
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X-Patchwork-Id: 13541842
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Date: Thu, 1 Feb 2024 21:52:20 +0000
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From: Daniel Golle <daniel@makrotopia.org>
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To: Bc-bocun Chen <bc-bocun.chen@mediatek.com>,
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Steven Liu <steven.liu@mediatek.com>,
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John Crispin <john@phrozen.org>,
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Chunfeng Yun <chunfeng.yun@mediatek.com>,
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Vinod Koul <vkoul@kernel.org>,
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Kishon Vijay Abraham I <kishon@kernel.org>,
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Rob Herring <robh@kernel.org>,
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Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
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Conor Dooley <conor+dt@kernel.org>,
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Daniel Golle <daniel@makrotopia.org>,
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Qingfang Deng <dqfext@gmail.com>,
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SkyLake Huang <SkyLake.Huang@mediatek.com>,
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Matthias Brugger <matthias.bgg@gmail.com>,
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AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>,
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Philipp Zabel <p.zabel@pengutronix.de>,
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linux-arm-kernel@lists.infradead.org,
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linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org,
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devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
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netdev@vger.kernel.org
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Subject: [PATCH 1/2] dt-bindings: phy: mediatek,xfi-tphy: add new bindings
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Message-ID:
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<702afb0c1246d95c90b22e57105304028bdd3083.1706823233.git.daniel@makrotopia.org>
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MIME-Version: 1.0
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Content-Disposition: inline
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List-Id: Linux Phy Mailing list <linux-phy.lists.infradead.org>
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Add bindings for the MediaTek XFI T-PHY Ethernet SerDes PHY found in the
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MediaTek MT7988 SoC which can operate at various interfaces modes:
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via USXGMII PCS:
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* USXGMII
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* 10GBase-R
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* 5GBase-R
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via LynxI SGMII PCS:
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* 2500Base-X
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* 1000Base-X
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* Cisco SGMII (MAC side)
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Signed-off-by: Daniel Golle <daniel@makrotopia.org>
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---
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.../bindings/phy/mediatek,xfi-tphy.yaml | 80 +++++++++++++++++++
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1 file changed, 80 insertions(+)
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create mode 100644 Documentation/devicetree/bindings/phy/mediatek,xfi-tphy.yaml
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/phy/mediatek,xfi-tphy.yaml
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@@ -0,0 +1,80 @@
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+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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+%YAML 1.2
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+---
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+$id: http://devicetree.org/schemas/phy/mediatek,xfi-tphy.yaml#
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+$schema: http://devicetree.org/meta-schemas/core.yaml#
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+
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+title: MediaTek XFI T-PHY
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+
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+maintainers:
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+ - Daniel Golle <daniel@makrotopia.org>
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+
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+description:
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+ The MediaTek XFI SerDes T-PHY provides the physical SerDes lanes
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+ used by the (10G/5G) USXGMII PCS and (1G/2.5G) LynxI PCS found in
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+ MediaTek's 10G-capabale SoCs.
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+
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+properties:
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+ $nodename:
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+ pattern: "^phy@[0-9a-f]+$"
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+
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+ compatible:
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+ const: mediatek,mt7988-xfi-tphy
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+
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+ reg:
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+ maxItems: 1
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+
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+ clocks:
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+ items:
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+ - description: XFI PHY clock
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+ - description: XFI register clock
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+
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+ clock-names:
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+ items:
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+ - const: xfipll
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+ - const: topxtal
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+
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+ resets:
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+ items:
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+ - description: PEXTP reset
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+
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+ mediatek,usxgmii-performance-errata:
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+ $ref: /schemas/types.yaml#/definitions/flag
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+ description:
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+ One instance of the T-PHY on MT7988 suffers from a performance
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+ problem in 10GBase-R mode which needs a work-around in the driver.
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+ The work-around is enabled using this flag.
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+
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+ "#phy-cells":
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+ const: 0
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+
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+required:
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+ - compatible
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+ - reg
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+ - clocks
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+ - clock-names
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+ - resets
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+ - "#phy-cells"
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+
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+additionalProperties: false
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+
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+examples:
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+ - |
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+ #include <dt-bindings/clock/mediatek,mt7988-clk.h>
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+ soc {
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+ #address-cells = <2>;
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+ #size-cells = <2>;
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+
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+ phy@11f20000 {
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+ compatible = "mediatek,mt7988-xfi-tphy";
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+ reg = <0 0x11f20000 0 0x10000>;
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+ clocks = <&xfi_pll CLK_XFIPLL_PLL_EN>,
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+ <&topckgen CLK_TOP_XFI_PHY_0_XTAL_SEL>;
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+ clock-names = "xfipll", "topxtal";
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+ resets = <&watchdog 14>;
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+ mediatek,usxgmii-performance-errata;
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+ #phy-cells = <0>;
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+ };
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+ };
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+
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+...
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