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58f4667a37
New stm32 target introduces support for stm32mp1 based devices.
For now it includes an initial support of the STM32MP135F-DK device.
The specifications bellow only list supported features.
Specifications
--------------
SOC: STM32MP135FAF7
RAM: 512 MiB
Storage: SD Card
Ethernet: 2x 100 Mbps
Wireless: 2.4GHz Cypress CYW43455 (802.11b/g/n)
LEDs: Heartbeat (Blue)
Buttons: 1x Reset, 1x User (USER2)
USB: 4x 2.0 Type-A
Signed-off-by: Thomas Richard <thomas.richard@bootlin.com>
Link: https://github.com/openwrt/openwrt/pull/16716
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
(cherry picked from commit 851e7f77e4)
Link: https://github.com/openwrt/openwrt/pull/17097
Signed-off-by: Petr Štetiar <ynezz@true.cz>
95 lines
3.1 KiB
Diff
95 lines
3.1 KiB
Diff
From 8d28aaf5d5dbfd1f452286fa6ac571df0bcf00ad Mon Sep 17 00:00:00 2001
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From: Christophe Roullier <christophe.roullier@foss.st.com>
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Date: Tue, 11 Jun 2024 10:36:06 +0200
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Subject: [PATCH 8/8] net: stmmac: dwmac-stm32: add management of stm32mp13 for
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stm32
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Add Ethernet support for STM32MP13.
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STM32MP13 is STM32 SOC with 2 GMACs instances.
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GMAC IP version is SNPS 4.20.
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GMAC IP configure with 1 RX and 1 TX queue.
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DMA HW capability register supported
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RX Checksum Offload Engine supported
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TX Checksum insertion supported
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Wake-Up On Lan supported
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TSO supported
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Signed-off-by: Christophe Roullier <christophe.roullier@foss.st.com>
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Reviewed-by: Marek Vasut <marex@denx.de>
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Signed-off-by: Paolo Abeni <pabeni@redhat.com>
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---
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.../net/ethernet/stmicro/stmmac/dwmac-stm32.c | 32 ++++++++++++++++---
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1 file changed, 28 insertions(+), 4 deletions(-)
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--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
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+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
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@@ -104,6 +104,7 @@ struct stm32_ops {
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int (*parse_data)(struct stm32_dwmac *dwmac,
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struct device *dev);
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bool clk_rx_enable_in_suspend;
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+ bool is_mp13;
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u32 syscfg_clr_off;
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};
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@@ -224,11 +225,18 @@ static int stm32mp1_configure_pmcr(struc
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{
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struct stm32_dwmac *dwmac = plat_dat->bsp_priv;
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u32 reg = dwmac->mode_reg;
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- int val;
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+ int val = 0;
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switch (plat_dat->mac_interface) {
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case PHY_INTERFACE_MODE_MII:
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- val = SYSCFG_PMCR_ETH_SEL_MII;
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+ /*
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+ * STM32MP15xx supports both MII and GMII, STM32MP13xx MII only.
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+ * SYSCFG_PMCSETR ETH_SELMII is present only on STM32MP15xx and
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+ * acts as a selector between 0:GMII and 1:MII. As STM32MP13xx
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+ * supports only MII, ETH_SELMII is not present.
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+ */
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+ if (!dwmac->ops->is_mp13) /* Select MII mode on STM32MP15xx */
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+ val |= SYSCFG_PMCR_ETH_SEL_MII;
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break;
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case PHY_INTERFACE_MODE_GMII:
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val = SYSCFG_PMCR_ETH_SEL_GMII;
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@@ -359,8 +367,12 @@ static int stm32_dwmac_parse_data(struct
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dwmac->mode_mask = SYSCFG_MP1_ETH_MASK;
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err = of_property_read_u32_index(np, "st,syscon", 2, &dwmac->mode_mask);
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- if (err)
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- dev_dbg(dev, "Warning sysconfig register mask not set\n");
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+ if (err) {
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+ if (dwmac->ops->is_mp13)
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+ dev_err(dev, "Sysconfig register mask must be set (%d)\n", err);
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+ else
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+ dev_dbg(dev, "Warning sysconfig register mask not set\n");
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+ }
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return err;
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}
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@@ -560,12 +572,24 @@ static struct stm32_ops stm32mp1_dwmac_d
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.resume = stm32mp1_resume,
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.parse_data = stm32mp1_parse_data,
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.syscfg_clr_off = 0x44,
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+ .is_mp13 = false,
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+ .clk_rx_enable_in_suspend = true
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+};
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+
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+static struct stm32_ops stm32mp13_dwmac_data = {
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+ .set_mode = stm32mp1_set_mode,
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+ .suspend = stm32mp1_suspend,
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+ .resume = stm32mp1_resume,
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+ .parse_data = stm32mp1_parse_data,
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+ .syscfg_clr_off = 0x08,
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+ .is_mp13 = true,
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.clk_rx_enable_in_suspend = true
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};
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static const struct of_device_id stm32_dwmac_match[] = {
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{ .compatible = "st,stm32-dwmac", .data = &stm32mcu_dwmac_data},
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{ .compatible = "st,stm32mp1-dwmac", .data = &stm32mp1_dwmac_data},
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+ { .compatible = "st,stm32mp13-dwmac", .data = &stm32mp13_dwmac_data},
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{ }
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};
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MODULE_DEVICE_TABLE(of, stm32_dwmac_match);
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