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58f4667a37
New stm32 target introduces support for stm32mp1 based devices.
For now it includes an initial support of the STM32MP135F-DK device.
The specifications bellow only list supported features.
Specifications
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SOC: STM32MP135FAF7
RAM: 512 MiB
Storage: SD Card
Ethernet: 2x 100 Mbps
Wireless: 2.4GHz Cypress CYW43455 (802.11b/g/n)
LEDs: Heartbeat (Blue)
Buttons: 1x Reset, 1x User (USER2)
USB: 4x 2.0 Type-A
Signed-off-by: Thomas Richard <thomas.richard@bootlin.com>
Link: https://github.com/openwrt/openwrt/pull/16716
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
(cherry picked from commit 851e7f77e4)
Link: https://github.com/openwrt/openwrt/pull/17097
Signed-off-by: Petr Štetiar <ynezz@true.cz>
133 lines
4.6 KiB
Diff
133 lines
4.6 KiB
Diff
From d23ba64e733580db2809e6f6dbf6f093fbd1b91b Mon Sep 17 00:00:00 2001
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From: Marek Vasut <marex@denx.de>
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Date: Tue, 11 Jun 2024 10:36:01 +0200
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Subject: [PATCH 4/8] net: stmmac: dwmac-stm32: Separate out external clock
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selector
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Pull the external clock selector into a separate function, to avoid
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conflating it with external clock rate validation and clock mux
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register configuration. This should make the code easier to read and
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understand.
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The dwmac->enable_eth_ck variable in the end indicates whether the MAC
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clock are supplied by external oscillator (true) or internal RCC clock
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IP (false). The dwmac->enable_eth_ck value is set based on multiple DT
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properties, some of them deprecated, some of them specific to bus mode.
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The following DT properties and variables are taken into account. In
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each case, if the property is present or true, MAC clock is supplied
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by external oscillator.
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- "st,ext-phyclk", assigned to variable dwmac->ext_phyclk
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- Used in any mode (MII/RMII/GMII/RGMII)
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- The only non-deprecated DT property of the three
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- "st,eth-clk-sel", assigned to variable dwmac->eth_clk_sel_reg
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- Valid only in GMII/RGMII mode
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- Deprecated property, backward compatibility only
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- "st,eth-ref-clk-sel", assigned to variable dwmac->eth_ref_clk_sel_reg
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- Valid only in RMII mode
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- Deprecated property, backward compatibility only
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The stm32mp1_select_ethck_external() function handles the aforementioned
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DT properties and sets dwmac->enable_eth_ck accordingly.
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The stm32mp1_set_mode() is adjusted to call stm32mp1_select_ethck_external()
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first and then only use dwmac->enable_eth_ck to determine hardware clock mux
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settings.
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No functional change intended.
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Signed-off-by: Marek Vasut <marex@denx.de>
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Signed-off-by: Christophe Roullier <christophe.roullier@foss.st.com>
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Signed-off-by: Paolo Abeni <pabeni@redhat.com>
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---
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.../net/ethernet/stmicro/stmmac/dwmac-stm32.c | 50 ++++++++++++++-----
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1 file changed, 38 insertions(+), 12 deletions(-)
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--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
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+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
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@@ -157,6 +157,37 @@ static int stm32_dwmac_init(struct plat_
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return stm32_dwmac_clk_enable(dwmac, resume);
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}
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+static int stm32mp1_select_ethck_external(struct plat_stmmacenet_data *plat_dat)
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+{
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+ struct stm32_dwmac *dwmac = plat_dat->bsp_priv;
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+
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+ switch (plat_dat->mac_interface) {
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+ case PHY_INTERFACE_MODE_MII:
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+ dwmac->enable_eth_ck = dwmac->ext_phyclk;
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+ return 0;
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+ case PHY_INTERFACE_MODE_GMII:
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+ dwmac->enable_eth_ck = dwmac->eth_clk_sel_reg ||
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+ dwmac->ext_phyclk;
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+ return 0;
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+ case PHY_INTERFACE_MODE_RMII:
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+ dwmac->enable_eth_ck = dwmac->eth_ref_clk_sel_reg ||
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+ dwmac->ext_phyclk;
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+ return 0;
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+ case PHY_INTERFACE_MODE_RGMII:
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+ case PHY_INTERFACE_MODE_RGMII_ID:
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+ case PHY_INTERFACE_MODE_RGMII_RXID:
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+ case PHY_INTERFACE_MODE_RGMII_TXID:
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+ dwmac->enable_eth_ck = dwmac->eth_clk_sel_reg ||
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+ dwmac->ext_phyclk;
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+ return 0;
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+ default:
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+ dwmac->enable_eth_ck = false;
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+ dev_err(dwmac->dev, "Mode %s not supported",
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+ phy_modes(plat_dat->mac_interface));
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+ return -EINVAL;
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+ }
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+}
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+
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static int stm32mp1_validate_ethck_rate(struct plat_stmmacenet_data *plat_dat)
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{
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struct stm32_dwmac *dwmac = plat_dat->bsp_priv;
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@@ -194,28 +225,25 @@ static int stm32mp1_set_mode(struct plat
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u32 reg = dwmac->mode_reg;
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int val, ret;
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- dwmac->enable_eth_ck = false;
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+ ret = stm32mp1_select_ethck_external(plat_dat);
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+ if (ret)
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+ return ret;
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+
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switch (plat_dat->mac_interface) {
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case PHY_INTERFACE_MODE_MII:
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- if (dwmac->ext_phyclk)
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- dwmac->enable_eth_ck = true;
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val = SYSCFG_PMCR_ETH_SEL_MII;
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pr_debug("SYSCFG init : PHY_INTERFACE_MODE_MII\n");
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break;
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case PHY_INTERFACE_MODE_GMII:
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val = SYSCFG_PMCR_ETH_SEL_GMII;
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- if (dwmac->eth_clk_sel_reg || dwmac->ext_phyclk) {
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- dwmac->enable_eth_ck = true;
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+ if (dwmac->enable_eth_ck)
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val |= SYSCFG_PMCR_ETH_CLK_SEL;
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- }
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pr_debug("SYSCFG init : PHY_INTERFACE_MODE_GMII\n");
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break;
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case PHY_INTERFACE_MODE_RMII:
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val = SYSCFG_PMCR_ETH_SEL_RMII;
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- if (dwmac->eth_ref_clk_sel_reg || dwmac->ext_phyclk) {
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- dwmac->enable_eth_ck = true;
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+ if (dwmac->enable_eth_ck)
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val |= SYSCFG_PMCR_ETH_REF_CLK_SEL;
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- }
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pr_debug("SYSCFG init : PHY_INTERFACE_MODE_RMII\n");
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break;
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case PHY_INTERFACE_MODE_RGMII:
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@@ -223,10 +251,8 @@ static int stm32mp1_set_mode(struct plat
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case PHY_INTERFACE_MODE_RGMII_RXID:
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case PHY_INTERFACE_MODE_RGMII_TXID:
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val = SYSCFG_PMCR_ETH_SEL_RGMII;
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- if (dwmac->eth_clk_sel_reg || dwmac->ext_phyclk) {
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- dwmac->enable_eth_ck = true;
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+ if (dwmac->enable_eth_ck)
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val |= SYSCFG_PMCR_ETH_CLK_SEL;
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- }
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pr_debug("SYSCFG init : PHY_INTERFACE_MODE_RGMII\n");
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break;
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default:
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