mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-21 06:33:41 +00:00
f003d732d7
Refreshed all patches. Removed upstreamed: - 031-v5.0-MIPS-BCM47XX-Setup-struct-device-for-the-SoC.patch - 142-jffs2-Fix-use-of-uninitialized-delayed_work-lockdep-.patch Removed upstreamed hunk in: - 800-bcma-get-SoC-device-struct-copy-its-DMA-params-to-th.patch Compile-tested on: cns3xxx Runtime-tested on: cns3xxx Signed-off-by: Koen Vandeputte <koen.vandeputte@ncentric.com>
83 lines
2.3 KiB
Diff
83 lines
2.3 KiB
Diff
From 203f17906ff45705fbdaa0430dbbc71142c2640f Mon Sep 17 00:00:00 2001
|
|
From: Hauke Mehrtens <hauke@hauke-m.de>
|
|
Date: Sat, 8 Dec 2018 21:45:53 +0100
|
|
Subject: [PATCH 1/3] MIPS: Compile post DMA flush only when needed
|
|
|
|
dma_sync_phys() is only called for some CPUs when a mapping is removed.
|
|
Add ARCH_HAS_SYNC_DMA_FOR_CPU only for the CPUs listed in
|
|
cpu_needs_post_dma_flush() which need this extra call and do not compile
|
|
this code in for other CPUs. We need this for R10000, R12000, BMIPS5000
|
|
CPUs and CPUs supporting MAAR which was introduced in MIPS32r5.
|
|
|
|
This will hopefully improve the performance of the not affected devices.
|
|
|
|
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
|
|
---
|
|
arch/mips/Kconfig | 6 +++++-
|
|
arch/mips/mm/dma-noncoherent.c | 2 ++
|
|
2 files changed, 7 insertions(+), 1 deletion(-)
|
|
|
|
--- a/arch/mips/Kconfig
|
|
+++ b/arch/mips/Kconfig
|
|
@@ -1116,7 +1116,6 @@ config DMA_PERDEV_COHERENT
|
|
config DMA_NONCOHERENT
|
|
bool
|
|
select ARCH_HAS_SYNC_DMA_FOR_DEVICE
|
|
- select ARCH_HAS_SYNC_DMA_FOR_CPU
|
|
select NEED_DMA_MAP_STATE
|
|
select DMA_NONCOHERENT_MMAP
|
|
select DMA_NONCOHERENT_CACHE_SYNC
|
|
@@ -1897,9 +1896,11 @@ config SYS_HAS_CPU_MIPS32_R3_5
|
|
|
|
config SYS_HAS_CPU_MIPS32_R5
|
|
bool
|
|
+ select ARCH_HAS_SYNC_DMA_FOR_CPU
|
|
|
|
config SYS_HAS_CPU_MIPS32_R6
|
|
bool
|
|
+ select ARCH_HAS_SYNC_DMA_FOR_CPU
|
|
|
|
config SYS_HAS_CPU_MIPS64_R1
|
|
bool
|
|
@@ -1909,6 +1910,7 @@ config SYS_HAS_CPU_MIPS64_R2
|
|
|
|
config SYS_HAS_CPU_MIPS64_R6
|
|
bool
|
|
+ select ARCH_HAS_SYNC_DMA_FOR_CPU
|
|
|
|
config SYS_HAS_CPU_R3000
|
|
bool
|
|
@@ -1945,6 +1947,7 @@ config SYS_HAS_CPU_R8000
|
|
|
|
config SYS_HAS_CPU_R10000
|
|
bool
|
|
+ select ARCH_HAS_SYNC_DMA_FOR_CPU
|
|
|
|
config SYS_HAS_CPU_RM7000
|
|
bool
|
|
@@ -1973,6 +1976,7 @@ config SYS_HAS_CPU_BMIPS4380
|
|
config SYS_HAS_CPU_BMIPS5000
|
|
bool
|
|
select SYS_HAS_CPU_BMIPS
|
|
+ select ARCH_HAS_SYNC_DMA_FOR_CPU
|
|
|
|
config SYS_HAS_CPU_XLR
|
|
bool
|
|
--- a/arch/mips/mm/dma-noncoherent.c
|
|
+++ b/arch/mips/mm/dma-noncoherent.c
|
|
@@ -191,12 +191,14 @@ void arch_sync_dma_for_device(struct dev
|
|
dma_sync_phys(paddr, size, dir);
|
|
}
|
|
|
|
+#ifdef CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU
|
|
void arch_sync_dma_for_cpu(struct device *dev, phys_addr_t paddr,
|
|
size_t size, enum dma_data_direction dir)
|
|
{
|
|
if (cpu_needs_post_dma_flush(dev))
|
|
dma_sync_phys(paddr, size, dir);
|
|
}
|
|
+#endif
|
|
|
|
void arch_dma_cache_sync(struct device *dev, void *vaddr, size_t size,
|
|
enum dma_data_direction direction)
|