mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-21 06:33:41 +00:00
f79af59383
Refresh backport patches with make target/linux/refresh. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
49 lines
1.8 KiB
Diff
49 lines
1.8 KiB
Diff
From 611e2dabb4b3243d176739fd6a5a34d007fa3f86 Mon Sep 17 00:00:00 2001
|
|
From: Daniel Golle <daniel@makrotopia.org>
|
|
Date: Tue, 14 Mar 2023 00:34:26 +0000
|
|
Subject: [PATCH 1/2] net: ethernet: mtk_eth_soc: reset PCS state
|
|
MIME-Version: 1.0
|
|
Content-Type: text/plain; charset=UTF-8
|
|
Content-Transfer-Encoding: 8bit
|
|
|
|
Reset the internal PCS state machine when changing interface mode.
|
|
This prevents confusing the state machine when changing interface
|
|
modes, e.g. from SGMII to 2500Base-X or vice-versa.
|
|
|
|
Fixes: 7e538372694b ("net: ethernet: mediatek: Re-add support SGMII")
|
|
Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
|
|
Tested-by: Bjørn Mork <bjorn@mork.no>
|
|
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
|
|
Signed-off-by: David S. Miller <davem@davemloft.net>
|
|
---
|
|
drivers/net/ethernet/mediatek/mtk_eth_soc.h | 4 ++++
|
|
drivers/net/ethernet/mediatek/mtk_sgmii.c | 4 ++++
|
|
2 files changed, 8 insertions(+)
|
|
|
|
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
|
|
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
|
|
@@ -542,6 +542,10 @@
|
|
#define SGMII_SEND_AN_ERROR_EN BIT(11)
|
|
#define SGMII_IF_MODE_MASK GENMASK(5, 1)
|
|
|
|
+/* Register to reset SGMII design */
|
|
+#define SGMII_RESERVED_0 0x34
|
|
+#define SGMII_SW_RESET BIT(0)
|
|
+
|
|
/* Register to set SGMII speed, ANA RG_ Control Signals III*/
|
|
#define SGMSYS_ANA_RG_CS3 0x2028
|
|
#define RG_PHY_SPEED_MASK (BIT(2) | BIT(3))
|
|
--- a/drivers/net/ethernet/mediatek/mtk_sgmii.c
|
|
+++ b/drivers/net/ethernet/mediatek/mtk_sgmii.c
|
|
@@ -88,6 +88,10 @@ static int mtk_pcs_config(struct phylink
|
|
regmap_update_bits(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL,
|
|
SGMII_PHYA_PWD, SGMII_PHYA_PWD);
|
|
|
|
+ /* Reset SGMII PCS state */
|
|
+ regmap_update_bits(mpcs->regmap, SGMII_RESERVED_0,
|
|
+ SGMII_SW_RESET, SGMII_SW_RESET);
|
|
+
|
|
if (interface == PHY_INTERFACE_MODE_2500BASEX)
|
|
rgc3 = RG_PHY_SPEED_3_125G;
|
|
else
|