openwrt/target/linux/ar71xx/patches-4.4/631-MIPS-ath79-wmac-enable-set-led-pin.patch
Sven Eckelmann b1d57dadb2 ar71xx: disable 40Mhz refclk for QCA953x
The "QCA9531 v2.0 802.11n 2x2 2.4 GHz Premium SOC for WLAN Platforms"
datasheet (80-Y7991-1 Rev. C - October 2014) doesn't specify support for a
40 Mhz reference clock. The register description for "Bootstrap Options"
(page 31) defines following states for the bit 4 (REF_CLK):

* 0 - CLK25 (default)
* 1 - (reserved)

Devices like the TP-Link CPE210 v2 has this bit set to 1 but is using a 25
Mhz reference clock. OpenWrt is still interpreted this bit as 40 Mhz and
then break the bootup of the system due to this incorrect interpretation.

Signed-off-by: Sven Eckelmann <sven@narfation.org>
[refreshed patches]
Signed-off-by: Piotr Dymacz <pepe2k@gmail.com>
2018-02-22 18:53:22 +01:00

25 lines
701 B
Diff

--- a/arch/mips/ath79/dev-wmac.c
+++ b/arch/mips/ath79/dev-wmac.c
@@ -406,6 +406,11 @@ void __init ath79_wmac_set_ext_lna_gpio(
ar934x_set_ext_lna_gpio(chain, gpio);
}
+void __init ath79_wmac_set_led_pin(int gpio)
+{
+ ath79_wmac_data.led_pin = gpio;
+}
+
void __init ath79_register_wmac(u8 *cal_data, u8 *mac_addr)
{
if (soc_is_ar913x())
--- a/arch/mips/ath79/dev-wmac.h
+++ b/arch/mips/ath79/dev-wmac.h
@@ -18,6 +18,7 @@ void ath79_wmac_disable_2ghz(void);
void ath79_wmac_disable_5ghz(void);
void ath79_wmac_set_tx_gain_buffalo(void);
void ath79_wmac_set_ext_lna_gpio(unsigned chain, int gpio);
+void ath79_wmac_set_led_pin(int gpio);
bool ar93xx_wmac_read_mac_address(u8 *dest);