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09eee2538e
Fix PCIe initialization by de-assertion of PCIe endpoint reset. Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com> Link: https://github.com/openwrt/openwrt/pull/15432 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
42 lines
1.3 KiB
Diff
42 lines
1.3 KiB
Diff
From 859c93981a8994ffa69967b44b247d2e7d6a01f1 Mon Sep 17 00:00:00 2001
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From: INAGAKI Hiroshi <musashino.open@gmail.com>
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Date: Fri, 26 Apr 2024 23:54:57 +0900
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Subject: [PATCH 2/2] MIPS: pci-ar724x: deassert the reset of PCIe endpoint
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Fix PCIe initialization by de-assertion of PCIe endpoint reset.
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Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
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---
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--- a/arch/mips/pci/pci-ar724x.c
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+++ b/arch/mips/pci/pci-ar724x.c
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@@ -25,6 +25,7 @@
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#define AR724X_PCI_APP_LTSSM_ENABLE BIT(0)
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+#define AR724X_PCI_RESET_EP_RESET_L BIT(2)
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#define AR724X_PCI_RESET_LINK_UP BIT(0)
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#define AR724X_PCI_INT_DEV0 BIT(14)
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@@ -340,7 +341,7 @@ static void ar724x_pci_irq_init(struct a
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static void ar724x_pci_hw_init(struct ar724x_pci_controller *apc)
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{
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- u32 ppl, app;
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+ u32 ppl, rst, app;
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int wait = 0;
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/* deassert PCIe host controller and PCIe PHY reset */
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@@ -370,6 +371,11 @@ static void ar724x_pci_hw_init(struct ar
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ath79_pll_wr(AR724X_PLL_REG_PCIE_CONFIG, ppl);
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}
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+ /* deassert the reset state of the PCIE endpoint */
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+ rst = __raw_readl(apc->ctrl_base + AR724X_PCI_REG_RESET);
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+ rst |= AR724X_PCI_RESET_EP_RESET_L;
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+ __raw_writel(rst, apc->ctrl_base + AR724X_PCI_REG_RESET);
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+
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/* set PCIE Application Control to ready */
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app = __raw_readl(apc->ctrl_base + AR724X_PCI_REG_APP);
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app |= AR724X_PCI_APP_LTSSM_ENABLE;
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