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047695a029
This reverts commit 51397d7d95
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There are some unresolved random crashes on WRT1900AC v1 that still need
to be sorted out
Signed-off-by: Felix Fietkau <nbd@nbd.name>
183 lines
5.3 KiB
Diff
183 lines
5.3 KiB
Diff
From b7dacf514e41d6efff0ccc170f660cc6dc2aeae2 Mon Sep 17 00:00:00 2001
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From: Russell King <rmk+kernel@arm.linux.org.uk>
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Date: Tue, 29 Sep 2015 15:17:39 +0100
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Subject: [PATCH 731/744] net: mvneta: add EEE support
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Add EEE support to mvneta. This allows us to enable the low power idle
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support at MAC level if there is a PHY attached through phylink which
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supports LPI. The appropriate ethtool support is provided to allow the
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feature to be controlled, including ethtool statistics for EEE wakeup
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errors.
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Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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---
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drivers/net/ethernet/marvell/mvneta.c | 87 +++++++++++++++++++++++++++++++++++
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1 file changed, 87 insertions(+)
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--- a/drivers/net/ethernet/marvell/mvneta.c
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+++ b/drivers/net/ethernet/marvell/mvneta.c
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@@ -243,6 +243,12 @@
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#define MVNETA_TXQ_TOKEN_SIZE_REG(q) (0x3e40 + ((q) << 2))
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#define MVNETA_TXQ_TOKEN_SIZE_MAX 0x7fffffff
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+#define MVNETA_LPI_CTRL_0 0x2cc0
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+#define MVNETA_LPI_CTRL_1 0x2cc4
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+#define MVNETA_LPI_REQUEST_ENABLE BIT(0)
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+#define MVNETA_LPI_CTRL_2 0x2cc8
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+#define MVNETA_LPI_STATUS 0x2ccc
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+
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#define MVNETA_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff
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/* Descriptor ring Macros */
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@@ -316,6 +322,11 @@
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#define MVNETA_RX_GET_BM_POOL_ID(rxd) \
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(((rxd)->status & MVNETA_RXD_BM_POOL_MASK) >> MVNETA_RXD_BM_POOL_SHIFT)
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+enum {
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+ ETHTOOL_STAT_EEE_WAKEUP,
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+ ETHTOOL_MAX_STATS,
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+};
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+
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struct mvneta_statistic {
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unsigned short offset;
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unsigned short type;
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@@ -324,6 +335,7 @@ struct mvneta_statistic {
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#define T_REG_32 32
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#define T_REG_64 64
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+#define T_SW 1
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static const struct mvneta_statistic mvneta_statistics[] = {
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{ 0x3000, T_REG_64, "good_octets_received", },
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@@ -358,6 +370,7 @@ static const struct mvneta_statistic mvn
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{ 0x304c, T_REG_32, "broadcast_frames_sent", },
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{ 0x3054, T_REG_32, "fc_sent", },
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{ 0x300c, T_REG_32, "internal_mac_transmit_err", },
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+ { ETHTOOL_STAT_EEE_WAKEUP, T_SW, "eee_wakeup_errors", },
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};
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struct mvneta_pcpu_stats {
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@@ -413,6 +426,10 @@ struct mvneta_port {
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struct mvneta_bm_pool *pool_short;
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int bm_win_id;
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+ bool eee_enabled;
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+ bool eee_active;
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+ bool tx_lpi_enabled;
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+
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u64 ethtool_stats[ARRAY_SIZE(mvneta_statistics)];
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u32 indir[MVNETA_RSS_LU_TABLE_SIZE];
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@@ -3276,6 +3293,18 @@ static void mvneta_mac_config(struct net
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mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, new_an);
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}
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+static void mvneta_set_eee(struct mvneta_port *pp, bool enable)
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+{
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+ u32 lpi_ctl1;
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+
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+ lpi_ctl1 = mvreg_read(pp, MVNETA_LPI_CTRL_1);
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+ if (enable)
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+ lpi_ctl1 |= MVNETA_LPI_REQUEST_ENABLE;
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+ else
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+ lpi_ctl1 &= ~MVNETA_LPI_REQUEST_ENABLE;
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+ mvreg_write(pp, MVNETA_LPI_CTRL_1, lpi_ctl1);
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+}
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+
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static void mvneta_mac_link_down(struct net_device *ndev, unsigned int mode)
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{
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struct mvneta_port *pp = netdev_priv(ndev);
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@@ -3289,6 +3318,9 @@ static void mvneta_mac_link_down(struct
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val |= MVNETA_GMAC_FORCE_LINK_DOWN;
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mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
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}
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+
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+ pp->eee_active = false;
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+ mvneta_set_eee(pp, false);
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}
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static void mvneta_mac_link_up(struct net_device *ndev, unsigned int mode,
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@@ -3305,6 +3337,11 @@ static void mvneta_mac_link_up(struct ne
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}
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mvneta_port_up(pp);
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+
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+ if (phy && pp->eee_enabled) {
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+ pp->eee_active = phy_init_eee(phy, 0) >= 0;
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+ mvneta_set_eee(pp, pp->eee_active && pp->tx_lpi_enabled);
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+ }
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}
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static const struct phylink_mac_ops mvneta_phylink_ops = {
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@@ -3744,6 +3781,13 @@ static void mvneta_ethtool_update_stats(
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val64 = (u64)high << 32 | low;
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pp->ethtool_stats[i] += val64;
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break;
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+ case T_SW:
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+ switch (s->offset) {
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+ case ETHTOOL_STAT_EEE_WAKEUP:
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+ val = phylink_get_eee_err(pp->phylink);
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+ break;
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+ }
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+ break;
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}
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}
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}
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@@ -3867,6 +3911,47 @@ static int mvneta_ethtool_get_rxfh(struc
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return 0;
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}
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+static int mvneta_ethtool_get_eee(struct net_device *dev,
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+ struct ethtool_eee *eee)
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+{
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+ struct mvneta_port *pp = netdev_priv(dev);
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+ u32 lpi_ctl0;
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+
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+ lpi_ctl0 = mvreg_read(pp, MVNETA_LPI_CTRL_0);
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+
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+ eee->eee_enabled = pp->eee_enabled;
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+ eee->eee_active = pp->eee_active;
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+ eee->tx_lpi_enabled = pp->tx_lpi_enabled;
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+ eee->tx_lpi_timer = (lpi_ctl0) >> 8; // * scale;
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+
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+ return phylink_ethtool_get_eee(pp->phylink, eee);
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+}
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+
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+static int mvneta_ethtool_set_eee(struct net_device *dev,
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+ struct ethtool_eee *eee)
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+{
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+ struct mvneta_port *pp = netdev_priv(dev);
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+ u32 lpi_ctl0;
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+
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+ /* The Armada 37x documents do not give limits for this other than
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+ * it being an 8-bit register. */
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+ if (eee->tx_lpi_enabled &&
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+ (eee->tx_lpi_timer < 0 || eee->tx_lpi_timer > 255))
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+ return -EINVAL;
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+
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+ lpi_ctl0 = mvreg_read(pp, MVNETA_LPI_CTRL_0);
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+ lpi_ctl0 &= ~(0xff << 8);
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+ lpi_ctl0 |= eee->tx_lpi_timer << 8;
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+ mvreg_write(pp, MVNETA_LPI_CTRL_0, lpi_ctl0);
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+
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+ pp->eee_enabled = eee->eee_enabled;
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+ pp->tx_lpi_enabled = eee->tx_lpi_enabled;
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+
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+ mvneta_set_eee(pp, eee->tx_lpi_enabled && eee->eee_enabled);
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+
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+ return phylink_ethtool_set_eee(pp->phylink, eee);
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+}
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+
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static const struct net_device_ops mvneta_netdev_ops = {
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.ndo_open = mvneta_open,
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.ndo_stop = mvneta_stop,
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@@ -3898,6 +3983,8 @@ const struct ethtool_ops mvneta_eth_tool
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.get_rxnfc = mvneta_ethtool_get_rxnfc,
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.get_rxfh = mvneta_ethtool_get_rxfh,
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.set_rxfh = mvneta_ethtool_set_rxfh,
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+ .get_eee = mvneta_ethtool_get_eee,
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+ .set_eee = mvneta_ethtool_set_eee,
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};
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/* Initialize hw */
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