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Follow the advise of Russell King allows to greatly improve the driver for RealTek's 1G and 2.5G Ethernet PHYs. The results are full/half duplex as well as Gbit master/slave property being read from PHY Specific Status Register (PHYSR), and fixes regarding link-partner advertisement. Fixes: #14504 Signed-off-by: Daniel Golle <daniel@makrotopia.org>
118 lines
3.2 KiB
Diff
118 lines
3.2 KiB
Diff
From 66d82d3f04623e9c096e12c10ca51141c345ee84 Mon Sep 17 00:00:00 2001
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From: Daniel Golle <daniel@makrotopia.org>
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Date: Tue, 8 Oct 2024 20:59:51 +0100
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Subject: [PATCH] net: phy: realtek: read duplex and gbit master from PHYSR
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register
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The PHYSR MMD register is present and defined equally for all RTL82xx
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Ethernet PHYs.
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Read duplex and gbit master bits from rtlgen_decode_speed() and rename
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it to rtlgen_decode_physr().
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Signed-off-by: Daniel Golle <daniel@makrotopia.org>
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---
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drivers/net/phy/realtek.c | 48 ++++++++++++++++++++++++++++++++-------
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1 file changed, 40 insertions(+), 8 deletions(-)
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--- a/drivers/net/phy/realtek.c
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+++ b/drivers/net/phy/realtek.c
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@@ -80,20 +80,24 @@
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#define RTL822X_VND2_GANLPAR 0xa414
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-#define RTL822X_VND2_PHYSR 0xa434
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-
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#define RTL8221B_PHYCR1 0xa430
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#define RTL8221B_PHYCR1_ALDPS_EN BIT(2)
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#define RTL8221B_PHYCR1_ALDPS_XTAL_OFF_EN BIT(12)
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+#define RTL_VND2_PHYSR 0xa434
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+#define RTL_VND2_PHYSR_LINK BIT(2)
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+#define RTL_VND2_PHYSR_DUPLEX BIT(3)
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+#define RTL_VND2_PHYSR_SPEEDL GENMASK(5, 4)
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+#define RTL_VND2_PHYSR_SPEEDH GENMASK(10, 9)
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+#define RTL_VND2_PHYSR_MASTER BIT(11)
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+#define RTL_VND2_PHYSR_SPEED_MASK (RTL_VND2_PHYSR_SPEEDL | RTL_VND2_PHYSR_SPEEDH)
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+
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#define RTL8366RB_POWER_SAVE 0x15
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#define RTL8366RB_POWER_SAVE_ON BIT(12)
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#define RTL9000A_GINMR 0x14
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#define RTL9000A_GINMR_LINK_STATUS BIT(4)
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-#define RTLGEN_SPEED_MASK 0x0630
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-
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#define RTL_GENERIC_PHYID 0x001cc800
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#define RTL_8211FVD_PHYID 0x001cc878
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#define RTL_8221B_VB_CG 0x001cc849
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@@ -661,9 +665,24 @@ static int rtl8366rb_config_init(struct
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}
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/* get actual speed to cover the downshift case */
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-static void rtlgen_decode_speed(struct phy_device *phydev, int val)
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+static void rtlgen_decode_physr(struct phy_device *phydev, int val)
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{
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- switch (val & RTLGEN_SPEED_MASK) {
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+ /* bit 2
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+ * 0: Link not OK
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+ * 1: Link OK
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+ */
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+ phydev->link = !!(val & RTL_VND2_PHYSR_LINK);
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+
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+ /* bit 3
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+ * 0: Half Duplex
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+ * 1: Full Duplex
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+ */
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+ if (val & RTL_VND2_PHYSR_DUPLEX)
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+ phydev->duplex = DUPLEX_FULL;
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+ else
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+ phydev->duplex = DUPLEX_HALF;
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+
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+ switch (val & RTL_VND2_PHYSR_SPEED_MASK) {
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case 0x0000:
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phydev->speed = SPEED_10;
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break;
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@@ -685,6 +704,19 @@ static void rtlgen_decode_speed(struct p
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default:
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break;
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}
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+
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+ /* bit 11
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+ * 0: Slave Mode
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+ * 1: Master Mode
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+ */
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+ if (phydev->speed >= 1000) {
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+ if (val & RTL_VND2_PHYSR_MASTER)
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+ phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER;
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+ else
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+ phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE;
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+ } else {
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+ phydev->master_slave_state = MASTER_SLAVE_STATE_UNSUPPORTED;
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+ }
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}
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static int rtlgen_read_status(struct phy_device *phydev)
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@@ -702,7 +734,7 @@ static int rtlgen_read_status(struct phy
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if (val < 0)
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return val;
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- rtlgen_decode_speed(phydev, val);
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+ rtlgen_decode_physr(phydev, val);
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return 0;
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}
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@@ -1030,11 +1062,11 @@ static int rtl822x_c45_read_status(struc
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return 0;
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/* Read actual speed from vendor register. */
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- val = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL822X_VND2_PHYSR);
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+ val = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL_VND2_PHYSR);
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if (val < 0)
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return val;
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- rtlgen_decode_speed(phydev, val);
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+ rtlgen_decode_physr(phydev, val);
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return 0;
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}
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