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95 lines
2.8 KiB
Diff
95 lines
2.8 KiB
Diff
From cd4a93d1532b2f0ffe508f7fb5d464ec49634dcd Mon Sep 17 00:00:00 2001
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From: Jes Sorensen <Jes.Sorensen@redhat.com>
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Date: Fri, 22 Jul 2016 13:55:24 -0400
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Subject: [PATCH] rtl8xxxu: Implement rtl8188e_set_tx_power()
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This matches the code used to set TX power on 8192eu, except it only
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handles path A.
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We should be able to consolidate this code.
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Signed-off-by: Jes Sorensen <Jes.Sorensen@redhat.com>
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---
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.../net/wireless/realtek/rtl8xxxu/rtl8xxxu_8188e.c | 63 ++++++++++++++++++++++
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1 file changed, 63 insertions(+)
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--- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8188e.c
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+++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8188e.c
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@@ -283,6 +283,68 @@ static struct rtl8xxxu_rfregval rtl8188e
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{0xff, 0xffffffff}
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};
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+int rtl8xxxu_8188e_channel_to_group(int channel)
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+{
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+ int group;
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+
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+ if (channel < 3)
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+ group = 0;
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+ else if (channel < 6)
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+ group = 1;
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+ else if (channel < 9)
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+ group = 2;
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+ else if (channel < 12)
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+ group = 3;
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+ else if (channel < 14)
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+ group = 4;
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+ else
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+ group = 5;
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+
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+ return group;
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+}
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+
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+static void
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+rtl8188e_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40)
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+{
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+ u32 val32, ofdm, mcs;
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+ u8 cck, ofdmbase, mcsbase;
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+ int group, tx_idx;
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+
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+ tx_idx = 0;
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+ group = rtl8xxxu_8188e_channel_to_group(channel);
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+
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+ cck = priv->cck_tx_power_index_A[group];
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+
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+ val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32);
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+ val32 &= 0xffff00ff;
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+ val32 |= (cck << 8);
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+ rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32);
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+
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+ val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
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+ val32 &= 0xff;
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+ val32 |= ((cck << 8) | (cck << 16) | (cck << 24));
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+ rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
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+
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+ ofdmbase = priv->ht40_1s_tx_power_index_A[group];
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+ ofdmbase += priv->ofdm_tx_power_diff[tx_idx].a;
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+ ofdm = ofdmbase | ofdmbase << 8 | ofdmbase << 16 | ofdmbase << 24;
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+
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+ rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06, ofdm);
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+ rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24, ofdm);
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+
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+ mcsbase = priv->ht40_1s_tx_power_index_A[group];
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+ if (ht40)
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+ mcsbase += priv->ht40_tx_power_diff[tx_idx++].a;
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+ else
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+ mcsbase += priv->ht20_tx_power_diff[tx_idx++].a;
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+ mcs = mcsbase | mcsbase << 8 | mcsbase << 16 | mcsbase << 24;
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+
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+ rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00, mcs);
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+ rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04, mcs);
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+ rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS11_MCS08, mcs);
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+ rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS15_MCS12, mcs);
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+}
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+
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void rtl8188eu_config_channel(struct ieee80211_hw *hw)
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{
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struct rtl8xxxu_priv *priv = hw->priv;
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@@ -1152,6 +1214,7 @@ struct rtl8xxxu_fileops rtl8188eu_fops =
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.enable_rf = rtl8188e_enable_rf,
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.disable_rf = rtl8188e_disable_rf,
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.usb_quirks = rtl8188e_usb_quirks,
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+ .set_tx_power = rtl8188e_set_tx_power,
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.update_rate_mask = rtl8xxxu_gen2_update_rate_mask,
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.report_connect = rtl8xxxu_gen2_report_connect,
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.writeN_block_size = 128,
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