mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-27 01:11:14 +00:00
41 lines
1.4 KiB
Diff
41 lines
1.4 KiB
Diff
From 061838d68d2c20acb5a57fbd92e3ed0ae906142e Mon Sep 17 00:00:00 2001
|
|
From: Jes Sorensen <Jes.Sorensen@redhat.com>
|
|
Date: Fri, 22 Jul 2016 12:56:30 -0400
|
|
Subject: [PATCH] rtl8xxxu: Initialize GPIO settings for 8188eu
|
|
|
|
This matches what the vendor driver does, but is actually opposite of
|
|
what it does for 8192eu.
|
|
|
|
Signed-off-by: Jes Sorensen <Jes.Sorensen@redhat.com>
|
|
---
|
|
drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c | 7 +++++++
|
|
drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h | 1 +
|
|
2 files changed, 8 insertions(+)
|
|
|
|
--- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c
|
|
+++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c
|
|
@@ -4210,6 +4210,13 @@ static int rtl8xxxu_init_device(struct i
|
|
* Reset USB mode switch setting
|
|
*/
|
|
rtl8xxxu_write8(priv, REG_ACLK_MON, 0x00);
|
|
+ } else if (priv->rtl_chip == RTL8188E) {
|
|
+ /*
|
|
+ * Init GPIO settings for 8188e
|
|
+ */
|
|
+ val8 = rtl8xxxu_read8(priv, REG_GPIO_MUXCFG);
|
|
+ val8 &= ~GPIO_MUXCFG_IO_SEL_ENBT;
|
|
+ rtl8xxxu_write8(priv, REG_GPIO_MUXCFG, val8);
|
|
}
|
|
|
|
rtl8723a_phy_lc_calibrate(priv);
|
|
--- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h
|
|
+++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h
|
|
@@ -143,6 +143,7 @@
|
|
#define REG_CAL_TIMER 0x003c
|
|
#define REG_ACLK_MON 0x003e
|
|
#define REG_GPIO_MUXCFG 0x0040
|
|
+#define GPIO_MUXCFG_IO_SEL_ENBT BIT(5)
|
|
#define REG_GPIO_IO_SEL 0x0042
|
|
#define REG_MAC_PINMUX_CFG 0x0043
|
|
#define REG_GPIO_PIN_CTRL 0x0044
|