mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-25 00:11:13 +00:00
b5f32064ed
Qualcomm Atheros IPQ807x is a modern WiSoC featuring: * Quad Core ARMv8 Cortex A-53 * @ 2.2 GHz (IPQ8072A/4A/6A/8A) Codename Hawkeye * @ 1.4 GHz (IPQ8070A/1A) Codename Acorn * Dual Band simultaneaous IEEE 802.11ax * 5G: 8x8/80 or 4x4/160MHz (IPQ8074A/8A) * 5G: 4x4/80 or 2x2/160MHz (IPQ8071A/2A/6A) * 5G: 2x2/80MHz (IPQ8070A) * 2G: 4x4/40MHz (IPQ8072A/4A/6A/8A) * 2G: 2x2/40MHz (IPQ8070A/1A) * 1x PSGMII via QCA8072/5 (Max 5x 1GbE ports) * 2x SGMII/USXGMII (1/2.5/5/10 GbE) on Hawkeye * 2x SGMII/USXGMII (1/2.5/5 GbE) on Acorn * DDR3L/4 32/16 bit up to 2400MT/s * SDIO 3.0/SD card 3.0/eMMC 5.1 * Dual USB 3.0 * One PCIe Gen2.1 and one PCIe Gen3.0 port (Single lane) * Parallel NAND (ONFI)/LCD * 6x QUP BLSP SPI/I2C/UART * I2S, PCM, and TDMA * HW PWM * 1.8V configurable GPIO * Companion PMP8074 PMIC via SPMI (GPIOS, RTC etc) Note that only v2 SOC models aka the ones ending with A suffix are supported, v1 models do not comply to the final 802.11ax and have lower clocks, lack the Gen3 PCIe etc. SoC itself has two UBI32 cores for the NSS offloading system, however currently no offloading is supported. Signed-off-by: Robert Marko <robimarko@gmail.com>
71 lines
1.7 KiB
Diff
71 lines
1.7 KiB
Diff
From ad2d07f71739351eeea1d8a120c0918e2c4b265f Mon Sep 17 00:00:00 2001
|
|
From: Robert Marko <robimarko@gmail.com>
|
|
Date: Wed, 22 Dec 2021 12:23:34 +0100
|
|
Subject: [PATCH] arm64: dts: ipq8074: add reserved memory nodes
|
|
|
|
IPQ8074 has multiple reserved memory ranges, if they are not defined
|
|
then weird things tend to happen, board hangs and resets when PCI or
|
|
WLAN is used etc.
|
|
|
|
So, to avoid all of that add the reserved memory nodes from the downstream
|
|
5.4 kernel from QCA.
|
|
This is their default layout meant for devices with 1GB of RAM, but
|
|
devices with lower ammounts can override the Q6 node.
|
|
|
|
Signed-off-by: Robert Marko <robimarko@gmail.com>
|
|
---
|
|
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 35 +++++++++++++++++++++++++++
|
|
1 file changed, 35 insertions(+)
|
|
|
|
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
|
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
|
@@ -85,6 +85,26 @@
|
|
#size-cells = <2>;
|
|
ranges;
|
|
|
|
+ nss@40000000 {
|
|
+ no-map;
|
|
+ reg = <0x0 0x40000000 0x0 0x01000000>;
|
|
+ };
|
|
+
|
|
+ tzapp_region: tzapp@4a400000 {
|
|
+ no-map;
|
|
+ reg = <0x0 0x4a400000 0x0 0x00200000>;
|
|
+ };
|
|
+
|
|
+ uboot@4a600000 {
|
|
+ no-map;
|
|
+ reg = <0x0 0x4a600000 0x0 0x00400000>;
|
|
+ };
|
|
+
|
|
+ sbl@4aa00000 {
|
|
+ no-map;
|
|
+ reg = <0x0 0x4aa00000 0x0 0x00100000>;
|
|
+ };
|
|
+
|
|
smem@4ab00000 {
|
|
compatible = "qcom,smem";
|
|
reg = <0x0 0x4ab00000 0x0 0x00100000>;
|
|
@@ -97,6 +117,21 @@
|
|
no-map;
|
|
reg = <0x0 0x4ac00000 0x0 0x00400000>;
|
|
};
|
|
+
|
|
+ q6_region: wcnss@4b000000 {
|
|
+ no-map;
|
|
+ reg = <0x0 0x4b000000 0x0 0x05f00000>;
|
|
+ };
|
|
+
|
|
+ q6_etr_region: q6_etr_dump@50f00000 {
|
|
+ no-map;
|
|
+ reg = <0x0 0x50f00000 0x0 0x00100000>;
|
|
+ };
|
|
+
|
|
+ m3_dump_region: m3_dump@51000000 {
|
|
+ no-map;
|
|
+ reg = <0x0 0x51000000 0x0 0x100000>;
|
|
+ };
|
|
};
|
|
|
|
firmware {
|