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aab466f422
Backport generic phylink validate series and make use of it for mtk_eth_soc Ethernet driver as well as mt7530 DSA driver. Signed-off-by: Daniel Golle <daniel@makrotopia.org>
255 lines
7.9 KiB
Diff
255 lines
7.9 KiB
Diff
From 901f3fbe13c3e56f0742e02717ccbfabbc95c463 Mon Sep 17 00:00:00 2001
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From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
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Date: Wed, 18 May 2022 15:55:22 +0100
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Subject: [PATCH 11/12] net: mtk_eth_soc: convert code structure to suit split
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PCS support
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Provide a mtk_pcs structure which encapsulates everything that the PCS
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functions need (the regmap and ana_rgc3 offset), and use this in the
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PCS functions. Provide shim functions to convert from the existing
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"mtk_sgmii_*" interface to the converted PCS functions.
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Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
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Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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---
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drivers/net/ethernet/mediatek/mtk_eth_soc.h | 15 ++-
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drivers/net/ethernet/mediatek/mtk_sgmii.c | 123 +++++++++++---------
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2 files changed, 79 insertions(+), 59 deletions(-)
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--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
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+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
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@@ -958,16 +958,23 @@ struct mtk_soc_data {
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/* currently no SoC has more than 2 macs */
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#define MTK_MAX_DEVS 2
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-/* struct mtk_sgmii - This is the structure holding sgmii regmap and its
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- * characteristics
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+/* struct mtk_pcs - This structure holds each sgmii regmap and associated
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+ * data
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* @regmap: The register map pointing at the range used to setup
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* SGMII modes
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* @ana_rgc3: The offset refers to register ANA_RGC3 related to regmap
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*/
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+struct mtk_pcs {
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+ struct regmap *regmap;
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+ u32 ana_rgc3;
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+};
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+/* struct mtk_sgmii - This is the structure holding sgmii regmap and its
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+ * characteristics
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+ * @pcs Array of individual PCS structures
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+ */
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struct mtk_sgmii {
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- struct regmap *regmap[MTK_MAX_DEVS];
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- u32 ana_rgc3;
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+ struct mtk_pcs pcs[MTK_MAX_DEVS];
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};
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/* struct mtk_eth - This is the main datasructure for holding the state
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--- a/drivers/net/ethernet/mediatek/mtk_sgmii.c
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+++ b/drivers/net/ethernet/mediatek/mtk_sgmii.c
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@@ -9,90 +9,71 @@
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#include <linux/mfd/syscon.h>
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#include <linux/of.h>
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+#include <linux/phylink.h>
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#include <linux/regmap.h>
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#include "mtk_eth_soc.h"
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-int mtk_sgmii_init(struct mtk_sgmii *ss, struct device_node *r, u32 ana_rgc3)
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-{
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- struct device_node *np;
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- int i;
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-
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- ss->ana_rgc3 = ana_rgc3;
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-
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- for (i = 0; i < MTK_MAX_DEVS; i++) {
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- np = of_parse_phandle(r, "mediatek,sgmiisys", i);
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- if (!np)
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- break;
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-
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- ss->regmap[i] = syscon_node_to_regmap(np);
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- of_node_put(np);
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- if (IS_ERR(ss->regmap[i]))
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- return PTR_ERR(ss->regmap[i]);
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- }
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-
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- return 0;
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-}
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-
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/* For SGMII interface mode */
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-static int mtk_sgmii_setup_mode_an(struct mtk_sgmii *ss, int id)
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+static int mtk_pcs_setup_mode_an(struct mtk_pcs *mpcs)
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{
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unsigned int val;
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- if (!ss->regmap[id])
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+ if (!mpcs->regmap)
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return -EINVAL;
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/* Setup the link timer and QPHY power up inside SGMIISYS */
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- regmap_write(ss->regmap[id], SGMSYS_PCS_LINK_TIMER,
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+ regmap_write(mpcs->regmap, SGMSYS_PCS_LINK_TIMER,
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SGMII_LINK_TIMER_DEFAULT);
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- regmap_read(ss->regmap[id], SGMSYS_SGMII_MODE, &val);
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+ regmap_read(mpcs->regmap, SGMSYS_SGMII_MODE, &val);
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val |= SGMII_REMOTE_FAULT_DIS;
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- regmap_write(ss->regmap[id], SGMSYS_SGMII_MODE, val);
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+ regmap_write(mpcs->regmap, SGMSYS_SGMII_MODE, val);
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- regmap_read(ss->regmap[id], SGMSYS_PCS_CONTROL_1, &val);
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+ regmap_read(mpcs->regmap, SGMSYS_PCS_CONTROL_1, &val);
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val |= SGMII_AN_RESTART;
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- regmap_write(ss->regmap[id], SGMSYS_PCS_CONTROL_1, val);
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+ regmap_write(mpcs->regmap, SGMSYS_PCS_CONTROL_1, val);
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- regmap_read(ss->regmap[id], SGMSYS_QPHY_PWR_STATE_CTRL, &val);
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+ regmap_read(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, &val);
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val &= ~SGMII_PHYA_PWD;
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- regmap_write(ss->regmap[id], SGMSYS_QPHY_PWR_STATE_CTRL, val);
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+ regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, val);
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return 0;
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+
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}
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/* For 1000BASE-X and 2500BASE-X interface modes, which operate at a
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* fixed speed.
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*/
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-static int mtk_sgmii_setup_mode_force(struct mtk_sgmii *ss, int id,
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- phy_interface_t interface)
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+static int mtk_pcs_setup_mode_force(struct mtk_pcs *mpcs,
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+ phy_interface_t interface)
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{
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unsigned int val;
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- if (!ss->regmap[id])
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+ if (!mpcs->regmap)
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return -EINVAL;
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- regmap_read(ss->regmap[id], ss->ana_rgc3, &val);
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+ regmap_read(mpcs->regmap, mpcs->ana_rgc3, &val);
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val &= ~RG_PHY_SPEED_MASK;
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if (interface == PHY_INTERFACE_MODE_2500BASEX)
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val |= RG_PHY_SPEED_3_125G;
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- regmap_write(ss->regmap[id], ss->ana_rgc3, val);
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+ regmap_write(mpcs->regmap, mpcs->ana_rgc3, val);
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/* Disable SGMII AN */
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- regmap_read(ss->regmap[id], SGMSYS_PCS_CONTROL_1, &val);
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+ regmap_read(mpcs->regmap, SGMSYS_PCS_CONTROL_1, &val);
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val &= ~SGMII_AN_ENABLE;
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- regmap_write(ss->regmap[id], SGMSYS_PCS_CONTROL_1, val);
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+ regmap_write(mpcs->regmap, SGMSYS_PCS_CONTROL_1, val);
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/* Set the speed etc but leave the duplex unchanged */
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- regmap_read(ss->regmap[id], SGMSYS_SGMII_MODE, &val);
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+ regmap_read(mpcs->regmap, SGMSYS_SGMII_MODE, &val);
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val &= SGMII_DUPLEX_FULL | ~SGMII_IF_MODE_MASK;
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val |= SGMII_SPEED_1000;
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- regmap_write(ss->regmap[id], SGMSYS_SGMII_MODE, val);
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+ regmap_write(mpcs->regmap, SGMSYS_SGMII_MODE, val);
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/* Release PHYA power down state */
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- regmap_read(ss->regmap[id], SGMSYS_QPHY_PWR_STATE_CTRL, &val);
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+ regmap_read(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, &val);
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val &= ~SGMII_PHYA_PWD;
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- regmap_write(ss->regmap[id], SGMSYS_QPHY_PWR_STATE_CTRL, val);
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+ regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, val);
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return 0;
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}
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@@ -100,44 +81,76 @@ static int mtk_sgmii_setup_mode_force(st
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int mtk_sgmii_config(struct mtk_sgmii *ss, int id, unsigned int mode,
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phy_interface_t interface)
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{
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+ struct mtk_pcs *mpcs = &ss->pcs[id];
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int err = 0;
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/* Setup SGMIISYS with the determined property */
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if (interface != PHY_INTERFACE_MODE_SGMII)
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- err = mtk_sgmii_setup_mode_force(ss, id, interface);
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+ err = mtk_pcs_setup_mode_force(mpcs, interface);
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else if (phylink_autoneg_inband(mode))
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- err = mtk_sgmii_setup_mode_an(ss, id);
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+ err = mtk_pcs_setup_mode_an(mpcs);
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return err;
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}
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-/* For 1000BASE-X and 2500BASE-X interface modes */
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-void mtk_sgmii_link_up(struct mtk_sgmii *ss, int id, int speed, int duplex)
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+static void mtk_pcs_restart_an(struct mtk_pcs *mpcs)
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+{
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+ unsigned int val;
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+
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+ if (!mpcs->regmap)
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+ return;
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+
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+ regmap_read(mpcs->regmap, SGMSYS_PCS_CONTROL_1, &val);
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+ val |= SGMII_AN_RESTART;
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+ regmap_write(mpcs->regmap, SGMSYS_PCS_CONTROL_1, val);
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+}
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+
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+static void mtk_pcs_link_up(struct mtk_pcs *mpcs, int speed, int duplex)
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{
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unsigned int val;
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/* SGMII force duplex setting */
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- regmap_read(ss->regmap[id], SGMSYS_SGMII_MODE, &val);
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+ regmap_read(mpcs->regmap, SGMSYS_SGMII_MODE, &val);
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val &= ~SGMII_DUPLEX_FULL;
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if (duplex == DUPLEX_FULL)
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val |= SGMII_DUPLEX_FULL;
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- regmap_write(ss->regmap[id], SGMSYS_SGMII_MODE, val);
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+ regmap_write(mpcs->regmap, SGMSYS_SGMII_MODE, val);
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+}
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+
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+/* For 1000BASE-X and 2500BASE-X interface modes */
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+void mtk_sgmii_link_up(struct mtk_sgmii *ss, int id, int speed, int duplex)
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+{
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+ mtk_pcs_link_up(&ss->pcs[id], speed, duplex);
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+}
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+
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+int mtk_sgmii_init(struct mtk_sgmii *ss, struct device_node *r, u32 ana_rgc3)
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+{
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+ struct device_node *np;
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+ int i;
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+
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+ for (i = 0; i < MTK_MAX_DEVS; i++) {
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+ np = of_parse_phandle(r, "mediatek,sgmiisys", i);
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+ if (!np)
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+ break;
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+
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+ ss->pcs[i].ana_rgc3 = ana_rgc3;
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+ ss->pcs[i].regmap = syscon_node_to_regmap(np);
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+ of_node_put(np);
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+ if (IS_ERR(ss->pcs[i].regmap))
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+ return PTR_ERR(ss->pcs[i].regmap);
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+ }
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+
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+ return 0;
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}
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void mtk_sgmii_restart_an(struct mtk_eth *eth, int mac_id)
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{
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- struct mtk_sgmii *ss = eth->sgmii;
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- unsigned int val, sid;
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+ unsigned int sid;
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/* Decide how GMAC and SGMIISYS be mapped */
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sid = (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_SGMII)) ?
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0 : mac_id;
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- if (!ss->regmap[sid])
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- return;
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-
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- regmap_read(ss->regmap[sid], SGMSYS_PCS_CONTROL_1, &val);
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- val |= SGMII_AN_RESTART;
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- regmap_write(ss->regmap[sid], SGMSYS_PCS_CONTROL_1, val);
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+ mtk_pcs_restart_an(ð->sgmii->pcs[sid]);
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}
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