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6c256218e59e wifi: mt76: dma: use napi_build_skb 679254c50f27 mt7915: add CONFIG_MT76_LEDS to cflags 15b9dd6b1b6a wifi: mt76: mt7915: call mt7915_mcu_set_thermal_throttling() only after init_work 8e5c21fe7c5c wifi: mt76: mt7915: rework mt7915_mcu_set_thermal_throttling 87cb74fe42d9 wifi: mt76: mt7915: rework mt7915_thermal_temp_store() c6f24b83eba5 wifi: mt76: mt7915: add error message in mt7915_thermal_set_cur_throttle_state() 99e96b89ee4d wifi: mt76: mt7915: add chip id condition in mt7915_check_eeprom() 833cd420480f wifi: mt76: mt7921: fix channel switch fail in monitor mode f1f8bae6092d wifi: mt76: mt7921: add ack signal support f47087a6dd62 wifi: mt76: mt7996: fix chainmask calculation in mt7996_set_antenna() 2f3b0acc1588 wifi: mt76: mt7996: update register for CFEND_RATE 7e9540dcbd70 wifi: mt76: mt7996: do not hardcode vht beamform cap a37e427d0959 wifi: mt76: connac: fix POWER_CTRL command name typo 98aa346042bd wifi: mt76: mt7915: remove BW160 and BW80+80 support 94fed6a43541 wifi: mt76: mt7921: fix invalid remain_on_channel duration 3c162384d80a wifi: mt76: introduce mt76_queue_is_wed_rx utility routine a409a9454587 wifi: mt76: mt7915: fix memory leak in mt7915_mcu_exit 8b27ecd3a684 wifi: mt76: mt7996: fix memory leak in mt7996_mcu_exit 683760461dd0 wifi: mt76: dma: free rx_head in mt76_dma_rx_cleanup 0c750cf08f85 wifi: mt76: dma: fix memory leak running mt76_dma_tx_cleanup 5de9ae29bea2 wifi: mt76: mt7915: avoid mcu_restart function pointer dad96dd3e62d wifi: mt76: mt7603: avoid mcu_restart function pointer 19d36dd9c8ea wifi: mt76: mt7615: avoid mcu_restart function pointer 6fe2c2383d3d wifi: mt76: mt7921: avoid mcu_restart function pointer 9df89143bf71 wifi: mt76: mt7915: get rid of wed rx_buf_ring page_frag_cache 8d51d11760cb wifi: mt76: fix switch default case in mt7996_reverse_frag0_hdr_trans 0d8057dbd51c wifi: mt76: mt7921u: add support for Comfast CF-952AX ddbf4e933d54 wifi: mt76: mt7915: set sku initial value to zero 06a8904e954e wifi: mt76: mt7915: wed: enable red per-band token drop 724a337caef9 wifi: mt76: mt7915: fix WED TxS reporting 747ca943a5bb wifi: mt76: add flexible polling wait-interval support 133d7859977a wifi: mt76: mt7921: reduce polling time in pmctrl 5fe319a0550e wifi: mt76: add memory barrier to SDIO queue kick 822f060b9d19 wifi: mt76: mt7921: fix rx filter incorrect by drv/fw inconsistent c6794954a723 wifi: mt76: mt7915: fix memory leak in mt7915_mmio_wed_init_rx_buf 9686cd7cc65c wifi: mt76: switch to page_pool allocator 04da4eaa8235 wifi: mt76: enable page_pool stats 1af4a911ebcb wifi: mt76: mt7915: release rxwi in mt7915_wed_release_rx_buf e8c10835cf06 wifi: mt76: fix compile error without CONFIG_PAGE_POOL_STATS 0cf0ede7cc42 net: ethernet: mtk_wed: add reset to rx_ring_setup callback 715b3ed9708a net: ethernet: mtk_wed: add reset to tx_ring_setup callback 9107381d0ff3 wifi: mt76: mt7921: fix error code of return in mt7921_acpi_read 36d2a5bf7802 wifi: mt76: mt7996: rely on mt76_connac2_mac_tx_rate_val c67f57d2cda2 wifi: mt76: dma: add reset to mt76_dma_wed_setup signature 3dace36e2941 wifi: mt76: dma: reset wed queues in mt76_dma_rx_reset 4b229d2da562 wifi: mt76: mt7915: add mt7915 wed reset callbacks f83958376085 wifi: mt76: mt7915: complete wed reset support 321edbb414dc wifi: mt76: mt7996: rely on mt76_connac_txp_common structure bdb7dc38a6d1 wifi: mt76: mt7996: rely on mt76_connac_txp_skb_unmap 8688756305c6 wifi: mt76: mt7996: rely on mt76_connac_tx_complete_skb fbf986dbd4c0 wifi: mt76: mt7996: rely on mt76_connac2_mac_decode_he_radiotap adc556cbce37 wifi: mt76: mt7996: avoid mcu_restart function pointer 5eb4e2303be4 wifi: mt76: remove __mt76_mcu_restart macro e7a61c5f70f5 wifi: mt76: add EHT phy type b375845abc10 wifi: mt76: connac: add CMD_CBW_320MHZ 68b17a243332 wifi: mt76: connac: add helpers for EHT capability 02ec1f61b3a2 wifi: mt76: connac: add cmd id related to EHT support 9209294cd81b wifi: mt76: increase wcid size to 1088 5e85136c9b2f wifi: mt76: add EHT rate stats for ethtool a171f672fdeb wifi: mt76: mt7996: add variants support eda8fd62c105 wifi: mt76: mt7996: add helpers for wtbl and interface limit 4a5a9f4cdc3b wifi: mt76: mt7996: rework capability init 06b73c155680 wifi: mt76: mt7996: add EHT capability init ae71a1b8294f wifi: mt76: mt7996: add support for EHT rate report 65bdfae2991d wifi: mt76: mt7996: enable EHT support in firmware b2360d59747c wifi: mt76: mt7996: add EHT beamforming support Signed-off-by: Felix Fietkau <nbd@nbd.name>
129 lines
4.1 KiB
Diff
129 lines
4.1 KiB
Diff
From e2e7f6e29c99a1c6afc0e0aa4b9ea80302d28720 Mon Sep 17 00:00:00 2001
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From: Daniel Golle <daniel@makrotopia.org>
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Date: Tue, 4 Jan 2022 12:07:46 +0000
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Subject: [PATCH 3/3] net: ethernet: mtk_eth_soc: implement Clause 45 MDIO
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access
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Implement read and write access to IEEE 802.3 Clause 45 Ethernet
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phy registers while making use of new mdiobus_c45_regad and
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mdiobus_c45_devad helpers.
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Tested on the Ubiquiti UniFi 6 LR access point featuring
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MediaTek MT7622BV WiSoC with Aquantia AQR112C.
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Signed-off-by: Daniel Golle <daniel@makrotopia.org>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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---
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drivers/net/ethernet/mediatek/mtk_eth_soc.c | 70 +++++++++++++++++----
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drivers/net/ethernet/mediatek/mtk_eth_soc.h | 3 +
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2 files changed, 60 insertions(+), 13 deletions(-)
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--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
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+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
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@@ -230,13 +230,35 @@ static int _mtk_mdio_write(struct mtk_et
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if (ret < 0)
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return ret;
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- mtk_w32(eth, PHY_IAC_ACCESS |
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- PHY_IAC_START_C22 |
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- PHY_IAC_CMD_WRITE |
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- PHY_IAC_REG(phy_reg) |
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- PHY_IAC_ADDR(phy_addr) |
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- PHY_IAC_DATA(write_data),
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- MTK_PHY_IAC);
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+ if (phy_reg & MII_ADDR_C45) {
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+ mtk_w32(eth, PHY_IAC_ACCESS |
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+ PHY_IAC_START_C45 |
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+ PHY_IAC_CMD_C45_ADDR |
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+ PHY_IAC_REG(mdiobus_c45_devad(phy_reg)) |
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+ PHY_IAC_ADDR(phy_addr) |
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+ PHY_IAC_DATA(mdiobus_c45_regad(phy_reg)),
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+ MTK_PHY_IAC);
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+
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+ ret = mtk_mdio_busy_wait(eth);
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+ if (ret < 0)
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+ return ret;
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+
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+ mtk_w32(eth, PHY_IAC_ACCESS |
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+ PHY_IAC_START_C45 |
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+ PHY_IAC_CMD_WRITE |
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+ PHY_IAC_REG(mdiobus_c45_devad(phy_reg)) |
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+ PHY_IAC_ADDR(phy_addr) |
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+ PHY_IAC_DATA(write_data),
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+ MTK_PHY_IAC);
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+ } else {
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+ mtk_w32(eth, PHY_IAC_ACCESS |
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+ PHY_IAC_START_C22 |
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+ PHY_IAC_CMD_WRITE |
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+ PHY_IAC_REG(phy_reg) |
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+ PHY_IAC_ADDR(phy_addr) |
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+ PHY_IAC_DATA(write_data),
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+ MTK_PHY_IAC);
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+ }
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ret = mtk_mdio_busy_wait(eth);
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if (ret < 0)
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@@ -253,12 +275,33 @@ static int _mtk_mdio_read(struct mtk_eth
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if (ret < 0)
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return ret;
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- mtk_w32(eth, PHY_IAC_ACCESS |
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- PHY_IAC_START_C22 |
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- PHY_IAC_CMD_C22_READ |
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- PHY_IAC_REG(phy_reg) |
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- PHY_IAC_ADDR(phy_addr),
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- MTK_PHY_IAC);
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+ if (phy_reg & MII_ADDR_C45) {
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+ mtk_w32(eth, PHY_IAC_ACCESS |
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+ PHY_IAC_START_C45 |
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+ PHY_IAC_CMD_C45_ADDR |
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+ PHY_IAC_REG(mdiobus_c45_devad(phy_reg)) |
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+ PHY_IAC_ADDR(phy_addr) |
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+ PHY_IAC_DATA(mdiobus_c45_regad(phy_reg)),
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+ MTK_PHY_IAC);
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+
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+ ret = mtk_mdio_busy_wait(eth);
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+ if (ret < 0)
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+ return ret;
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+
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+ mtk_w32(eth, PHY_IAC_ACCESS |
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+ PHY_IAC_START_C45 |
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+ PHY_IAC_CMD_C45_READ |
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+ PHY_IAC_REG(mdiobus_c45_devad(phy_reg)) |
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+ PHY_IAC_ADDR(phy_addr),
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+ MTK_PHY_IAC);
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+ } else {
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+ mtk_w32(eth, PHY_IAC_ACCESS |
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+ PHY_IAC_START_C22 |
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+ PHY_IAC_CMD_C22_READ |
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+ PHY_IAC_REG(phy_reg) |
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+ PHY_IAC_ADDR(phy_addr),
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+ MTK_PHY_IAC);
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+ }
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ret = mtk_mdio_busy_wait(eth);
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if (ret < 0)
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@@ -726,6 +769,7 @@ static int mtk_mdio_init(struct mtk_eth
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eth->mii_bus->name = "mdio";
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eth->mii_bus->read = mtk_mdio_read;
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eth->mii_bus->write = mtk_mdio_write;
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+ eth->mii_bus->probe_capabilities = MDIOBUS_C22_C45;
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eth->mii_bus->priv = eth;
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eth->mii_bus->parent = eth->dev;
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--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
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+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
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@@ -369,9 +369,12 @@
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#define PHY_IAC_ADDR_MASK GENMASK(24, 20)
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#define PHY_IAC_ADDR(x) FIELD_PREP(PHY_IAC_ADDR_MASK, (x))
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#define PHY_IAC_CMD_MASK GENMASK(19, 18)
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+#define PHY_IAC_CMD_C45_ADDR FIELD_PREP(PHY_IAC_CMD_MASK, 0)
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#define PHY_IAC_CMD_WRITE FIELD_PREP(PHY_IAC_CMD_MASK, 1)
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#define PHY_IAC_CMD_C22_READ FIELD_PREP(PHY_IAC_CMD_MASK, 2)
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+#define PHY_IAC_CMD_C45_READ FIELD_PREP(PHY_IAC_CMD_MASK, 3)
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#define PHY_IAC_START_MASK GENMASK(17, 16)
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+#define PHY_IAC_START_C45 FIELD_PREP(PHY_IAC_START_MASK, 0)
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#define PHY_IAC_START_C22 FIELD_PREP(PHY_IAC_START_MASK, 1)
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#define PHY_IAC_DATA_MASK GENMASK(15, 0)
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#define PHY_IAC_DATA(x) FIELD_PREP(PHY_IAC_DATA_MASK, (x))
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