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74 lines
2.3 KiB
Diff
74 lines
2.3 KiB
Diff
From c43e4b52cbf2267047f67c9f65de18ee1ab8bfa2 Mon Sep 17 00:00:00 2001
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From: Ray Jui <rjui@broadcom.com>
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Date: Wed, 27 Jan 2016 16:52:24 -0600
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Subject: [PATCH] PCI: iproc: Fix BCMA PCIe bus scanning regression
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Commit 943ebae781f5 ("PCI: iproc: Add PAXC interface support") causes
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regression on EP device detection on BCMA based platforms.
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Fix the issue by allowing multiple devices to be configured on the same
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bus, for all PAXB based child buses. In addition, add a check to prevent
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non-zero function from being used on bus 0 (root bus).
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Fixes: 943ebae781f5 ("PCI: iproc: Add PAXC interface support")
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Reported-by: Rafal Milecki <zajec5@gmail.com>
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Signed-off-by: Ray Jui <rjui@broadcom.com>
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Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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---
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drivers/pci/host/pcie-iproc.c | 28 +++++++++++-----------------
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1 file changed, 11 insertions(+), 17 deletions(-)
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--- a/drivers/pci/host/pcie-iproc.c
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+++ b/drivers/pci/host/pcie-iproc.c
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@@ -170,20 +170,6 @@ static inline void iproc_pcie_ob_write(s
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writel(val, pcie->base + offset + (window * 8));
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}
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-static inline bool iproc_pcie_device_is_valid(struct iproc_pcie *pcie,
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- unsigned int slot,
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- unsigned int fn)
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-{
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- if (slot > 0)
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- return false;
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-
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- /* PAXC can only support limited number of functions */
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- if (pcie->type == IPROC_PCIE_PAXC && fn >= MAX_NUM_PAXC_PF)
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- return false;
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-
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- return true;
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-}
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-
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/**
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* Note access to the configuration registers are protected at the higher layer
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* by 'pci_lock' in drivers/pci/access.c
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@@ -199,11 +185,11 @@ static void __iomem *iproc_pcie_map_cfg_
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u32 val;
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u16 offset;
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- if (!iproc_pcie_device_is_valid(pcie, slot, fn))
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- return NULL;
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-
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/* root complex access */
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if (busno == 0) {
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+ if (slot > 0 || fn > 0)
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+ return NULL;
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+
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iproc_pcie_write_reg(pcie, IPROC_PCIE_CFG_IND_ADDR,
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where & CFG_IND_ADDR_MASK);
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offset = iproc_pcie_reg_offset(pcie, IPROC_PCIE_CFG_IND_DATA);
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@@ -213,6 +199,14 @@ static void __iomem *iproc_pcie_map_cfg_
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return (pcie->base + offset);
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}
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+ /*
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+ * PAXC is connected to an internally emulated EP within the SoC. It
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+ * allows only one device and supports a limited number of functions.
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+ */
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+ if (pcie->type == IPROC_PCIE_PAXC)
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+ if (slot > 0 || fn >= MAX_NUM_PAXC_PF)
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+ return NULL;
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+
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/* EP device access */
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val = (busno << CFG_ADDR_BUS_NUM_SHIFT) |
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(slot << CFG_ADDR_DEV_NUM_SHIFT) |
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