mirror of
https://github.com/openwrt/openwrt.git
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62b7f5931c
bcm2708: boot tested on RPi B+ v1.2
bcm2709: boot tested on RPi 3B v1.2 and RPi 4B v1.1 4G
bcm2710: boot tested on RPi 3B v1.2
bcm2711: boot tested on RPi 4B v1.1 4G
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
(cherry-picked from commit f07e572f64)
150 lines
5.8 KiB
Diff
150 lines
5.8 KiB
Diff
From 9b899afd231b7dde6084092cf46dd15c05ed8a5c Mon Sep 17 00:00:00 2001
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From: Phil Elwell <phil@raspberrypi.com>
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Date: Tue, 27 Oct 2020 12:11:56 +0000
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Subject: [PATCH] dwc_otg: Fix more build warnings
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Signed-off-by: Phil Elwell <phil@raspberrypi.com>
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---
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drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c | 10 +++++----
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drivers/usb/host/dwc_otg/dwc_otg_hcd.c | 23 ++++++++++++++-------
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drivers/usb/host/dwc_otg/dwc_otg_hcd_ddma.c | 3 ++-
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drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c | 8 +++----
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4 files changed, 27 insertions(+), 17 deletions(-)
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--- a/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c
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+++ b/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c
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@@ -240,7 +240,8 @@ static int notrace fiq_increment_dma_buf
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hcdma_data_t hcdma;
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int i = st->channel[n].dma_info.index;
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int len;
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- struct fiq_dma_blob *blob = (struct fiq_dma_blob *) st->dma_base;
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+ struct fiq_dma_blob *blob =
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+ (struct fiq_dma_blob *)(uintptr_t)st->dma_base;
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len = fiq_get_xfer_len(st, n);
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fiq_print(FIQDBG_INT, st, "LEN: %03d", len);
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@@ -249,7 +250,7 @@ static int notrace fiq_increment_dma_buf
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if (i > 6)
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BUG();
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- hcdma.d32 = (dma_addr_t) &blob->channel[n].index[i].buf[0];
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+ hcdma.d32 = (u32)(uintptr_t)&blob->channel[n].index[i].buf[0];
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FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HC_DMA, hcdma.d32);
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st->channel[n].dma_info.index = i;
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return 0;
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@@ -289,7 +290,8 @@ static int notrace fiq_iso_out_advance(s
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hcsplt_data_t hcsplt;
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hctsiz_data_t hctsiz;
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hcdma_data_t hcdma;
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- struct fiq_dma_blob *blob = (struct fiq_dma_blob *) st->dma_base;
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+ struct fiq_dma_blob *blob =
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+ (struct fiq_dma_blob *)(uintptr_t)st->dma_base;
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int last = 0;
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int i = st->channel[n].dma_info.index;
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@@ -301,7 +303,7 @@ static int notrace fiq_iso_out_advance(s
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last = 1;
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/* New DMA address - address of bounce buffer referred to in index */
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- hcdma.d32 = (dma_addr_t) blob->channel[n].index[i].buf;
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+ hcdma.d32 = (u32)(uintptr_t)blob->channel[n].index[i].buf;
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//hcdma.d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HC_DMA);
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//hcdma.d32 += st->channel[n].dma_info.slot_len[i];
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fiq_print(FIQDBG_INT, st, "LAST: %01d ", last);
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--- a/drivers/usb/host/dwc_otg/dwc_otg_hcd.c
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+++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd.c
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@@ -1268,7 +1268,8 @@ static void assign_and_init_hc(dwc_otg_h
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hc->multi_count = 1;
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if (hcd->core_if->dma_enable) {
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- hc->xfer_buff = (uint8_t *) urb->dma + urb->actual_length;
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+ hc->xfer_buff =
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+ (uint8_t *)(uintptr_t)urb->dma + urb->actual_length;
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/* For non-dword aligned case */
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if (((unsigned long)hc->xfer_buff & 0x3)
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@@ -1312,7 +1313,8 @@ static void assign_and_init_hc(dwc_otg_h
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hc->ep_is_in = 0;
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hc->data_pid_start = DWC_OTG_HC_PID_SETUP;
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if (hcd->core_if->dma_enable) {
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- hc->xfer_buff = (uint8_t *) urb->setup_dma;
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+ hc->xfer_buff =
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+ (uint8_t *)(uintptr_t)urb->setup_dma;
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} else {
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hc->xfer_buff = (uint8_t *) urb->setup_packet;
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}
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@@ -1360,7 +1362,8 @@ static void assign_and_init_hc(dwc_otg_h
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hc->xfer_len = 0;
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if (hcd->core_if->dma_enable) {
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- hc->xfer_buff = (uint8_t *) hcd->status_buf_dma;
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+ hc->xfer_buff = (uint8_t *)
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+ (uintptr_t)hcd->status_buf_dma;
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} else {
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hc->xfer_buff = (uint8_t *) hcd->status_buf;
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}
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@@ -1388,7 +1391,7 @@ static void assign_and_init_hc(dwc_otg_h
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frame_desc->status = 0;
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if (hcd->core_if->dma_enable) {
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- hc->xfer_buff = (uint8_t *) urb->dma;
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+ hc->xfer_buff = (uint8_t *)(uintptr_t)urb->dma;
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} else {
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hc->xfer_buff = (uint8_t *) urb->buf;
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}
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@@ -1569,8 +1572,10 @@ int fiq_fsm_setup_periodic_dma(dwc_otg_h
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* Pointer arithmetic on hcd->fiq_state->dma_base (a dma_addr_t)
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* to point it to the correct offset in the allocated buffers.
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*/
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- blob = (struct fiq_dma_blob *) hcd->fiq_state->dma_base;
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- st->hcdma_copy.d32 = (dma_addr_t) blob->channel[hc->hc_num].index[0].buf;
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+ blob = (struct fiq_dma_blob *)
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+ (uintptr_t)hcd->fiq_state->dma_base;
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+ st->hcdma_copy.d32 =(u32)(uintptr_t)
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+ blob->channel[hc->hc_num].index[0].buf;
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/* Calculate the max number of CSPLITS such that the FIQ can time out
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* a transaction if it fails.
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@@ -1625,8 +1630,10 @@ int fiq_fsm_setup_periodic_dma(dwc_otg_h
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* dma_addr_t) to point it to the correct offset in the
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* allocated buffers.
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*/
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- blob = (struct fiq_dma_blob *) hcd->fiq_state->dma_base;
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- st->hcdma_copy.d32 = (dma_addr_t) blob->channel[hc->hc_num].index[0].buf;
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+ blob = (struct fiq_dma_blob *)
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+ (uintptr_t)hcd->fiq_state->dma_base;
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+ st->hcdma_copy.d32 = (u32)(uintptr_t)
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+ blob->channel[hc->hc_num].index[0].buf;
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/* fixup xfersize to the actual packet size */
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st->hctsiz_copy.b.pid = 0;
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--- a/drivers/usb/host/dwc_otg/dwc_otg_hcd_ddma.c
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+++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd_ddma.c
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@@ -620,7 +620,8 @@ static void init_non_isoc_dma_desc(dwc_o
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if (n_desc) {
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/* SG request - more than 1 QTDs */
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- hc->xfer_buff = (uint8_t *)qtd->urb->dma + qtd->urb->actual_length;
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+ hc->xfer_buff = (uint8_t *)(uintptr_t)qtd->urb->dma +
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+ qtd->urb->actual_length;
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hc->xfer_len = qtd->urb->length - qtd->urb->actual_length;
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}
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--- a/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c
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+++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c
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@@ -1857,10 +1857,10 @@ static int32_t handle_hc_ahberr_intr(dwc
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DWC_ERROR(" Max packet size: %d\n",
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dwc_otg_hcd_get_mps(&urb->pipe_info));
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DWC_ERROR(" Data buffer length: %d\n", urb->length);
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- DWC_ERROR(" Transfer buffer: %p, Transfer DMA: %p\n",
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- urb->buf, (void *)urb->dma);
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- DWC_ERROR(" Setup buffer: %p, Setup DMA: %p\n",
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- urb->setup_packet, (void *)urb->setup_dma);
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+ DWC_ERROR(" Transfer buffer: %p, Transfer DMA: %pad\n",
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+ urb->buf, &urb->dma);
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+ DWC_ERROR(" Setup buffer: %p, Setup DMA: %pad\n",
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+ urb->setup_packet, &urb->setup_dma);
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DWC_ERROR(" Interval: %d\n", urb->interval);
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/* Core haltes the channel for Descriptor DMA mode */
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