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62b7f5931c
bcm2708: boot tested on RPi B+ v1.2
bcm2709: boot tested on RPi 3B v1.2 and RPi 4B v1.1 4G
bcm2710: boot tested on RPi 3B v1.2
bcm2711: boot tested on RPi 4B v1.1 4G
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
(cherry-picked from commit f07e572f64)
265 lines
6.9 KiB
Diff
265 lines
6.9 KiB
Diff
From c175c735869b0dfa8c21fc57d5bd02ca370f9117 Mon Sep 17 00:00:00 2001
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From: Dave Stevenson <dave.stevenson@raspberrypi.com>
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Date: Thu, 25 Jun 2020 08:28:51 +0100
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Subject: [PATCH] media: i2c: imx290: Add support for 74.25MHz clock
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The existing driver only supported a clock of 37.125MHz, but the
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sensor also supports 74.25MHz.
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Add the relevant register modifications to support this alternate
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clock frequency.
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Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
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---
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drivers/media/i2c/imx290.c | 119 ++++++++++++++++++++++++++++++-------
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1 file changed, 97 insertions(+), 22 deletions(-)
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--- a/drivers/media/i2c/imx290.c
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+++ b/drivers/media/i2c/imx290.c
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@@ -1,6 +1,10 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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- * Sony IMX290 CMOS Image Sensor Driver
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+ * Sony IMX290/327 CMOS Image Sensor Driver
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+ *
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+ * The IMX290 and IMX327 are very similar 1920x1080 1/2.8 CMOS image sensors.
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+ * IMX327 can support up to 60fps, whilst IMX290 support up to 120fps (only
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+ * 10bit and when connected over 4 CSI-2 lanes).
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*
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* Copyright (C) 2019 FRAMOS GmbH.
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*
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@@ -22,6 +26,11 @@
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#include <media/v4l2-fwnode.h>
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#include <media/v4l2-subdev.h>
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+enum imx290_clk_index {
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+ CLK_37_125,
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+ CLK_74_25,
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+};
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+
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#define IMX290_STANDBY 0x3000
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#define IMX290_REGHOLD 0x3001
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#define IMX290_XMSTA 0x3002
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@@ -60,11 +69,16 @@ struct imx290_mode {
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const struct imx290_regval *data;
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u32 data_size;
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+
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+ /* Clock setup can vary. Index as enum imx290_clk_index */
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+ const struct imx290_regval *clk_data[2];
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+ u32 clk_size;
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};
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struct imx290 {
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struct device *dev;
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struct clk *xclk;
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+ u32 xclk_freq;
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struct regmap *regmap;
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u8 nlanes;
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u8 bpp;
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@@ -116,8 +130,6 @@ static const struct imx290_regval imx290
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{ 0x3018, 0x65 },
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{ 0x3019, 0x04 },
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{ 0x301a, 0x00 },
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- { 0x3444, 0x20 },
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- { 0x3445, 0x25 },
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{ 0x303a, 0x0c },
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{ 0x3040, 0x00 },
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{ 0x3041, 0x00 },
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@@ -171,6 +183,30 @@ static const struct imx290_regval imx290
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{ 0x33b3, 0x04 },
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};
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+static const struct imx290_regval imx290_37_125mhz_clock_1080p[] = {
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+ { 0x305c, 0x18 },
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+ { 0x305d, 0x03 },
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+ { 0x305e, 0x20 },
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+ { 0x305f, 0x01 },
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+ { 0x315e, 0x1a },
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+ { 0x3164, 0x1a },
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+ { 0x3444, 0x20 },
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+ { 0x3445, 0x25 },
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+ { 0x3480, 0x49 },
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+};
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+
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+static const struct imx290_regval imx290_74_250mhz_clock_1080p[] = {
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+ { 0x305c, 0x0c },
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+ { 0x305d, 0x03 },
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+ { 0x305e, 0x10 },
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+ { 0x305f, 0x01 },
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+ { 0x315e, 0x1b },
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+ { 0x3164, 0x1b },
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+ { 0x3444, 0x40 },
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+ { 0x3445, 0x4a },
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+ { 0x3480, 0x92 },
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+};
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+
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static const struct imx290_regval imx290_1080p_settings[] = {
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/* mode settings */
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{ 0x3007, 0x00 },
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@@ -182,13 +218,6 @@ static const struct imx290_regval imx290
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{ 0x3419, 0x04 },
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{ 0x3012, 0x64 },
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{ 0x3013, 0x00 },
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- { 0x305c, 0x18 },
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- { 0x305d, 0x03 },
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- { 0x305e, 0x20 },
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- { 0x305f, 0x01 },
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- { 0x315e, 0x1a },
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- { 0x3164, 0x1a },
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- { 0x3480, 0x49 },
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/* data rate settings */
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{ 0x3405, 0x10 },
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{ 0x3446, 0x57 },
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@@ -209,6 +238,30 @@ static const struct imx290_regval imx290
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{ 0x3455, 0x00 },
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};
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+static const struct imx290_regval imx290_37_125mhz_clock_720p[] = {
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+ { 0x305c, 0x20 },
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+ { 0x305d, 0x00 },
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+ { 0x305e, 0x20 },
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+ { 0x305f, 0x01 },
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+ { 0x315e, 0x1a },
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+ { 0x3164, 0x1a },
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+ { 0x3444, 0x20 },
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+ { 0x3445, 0x25 },
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+ { 0x3480, 0x49 },
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+};
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+
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+static const struct imx290_regval imx290_74_250mhz_clock_720p[] = {
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+ { 0x305c, 0x10 },
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+ { 0x305d, 0x00 },
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+ { 0x305e, 0x10 },
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+ { 0x305f, 0x01 },
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+ { 0x315e, 0x1b },
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+ { 0x3164, 0x1b },
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+ { 0x3444, 0x40 },
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+ { 0x3445, 0x4a },
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+ { 0x3480, 0x92 },
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+};
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+
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static const struct imx290_regval imx290_720p_settings[] = {
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/* mode settings */
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{ 0x3007, 0x10 },
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@@ -220,13 +273,6 @@ static const struct imx290_regval imx290
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{ 0x3419, 0x02 },
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{ 0x3012, 0x64 },
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{ 0x3013, 0x00 },
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- { 0x305c, 0x20 },
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- { 0x305d, 0x00 },
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- { 0x305e, 0x20 },
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- { 0x305f, 0x01 },
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- { 0x315e, 0x1a },
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- { 0x3164, 0x1a },
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- { 0x3480, 0x49 },
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/* data rate settings */
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{ 0x3405, 0x10 },
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{ 0x3446, 0x4f },
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@@ -312,6 +358,11 @@ static const struct imx290_mode imx290_m
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.link_freq_index = FREQ_INDEX_1080P,
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.data = imx290_1080p_settings,
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.data_size = ARRAY_SIZE(imx290_1080p_settings),
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+ .clk_data = {
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+ [CLK_37_125] = imx290_37_125mhz_clock_1080p,
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+ [CLK_74_25] = imx290_74_250mhz_clock_1080p,
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+ },
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+ .clk_size = ARRAY_SIZE(imx290_37_125mhz_clock_1080p),
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},
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{
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.width = 1280,
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@@ -320,6 +371,11 @@ static const struct imx290_mode imx290_m
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.link_freq_index = FREQ_INDEX_720P,
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.data = imx290_720p_settings,
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.data_size = ARRAY_SIZE(imx290_720p_settings),
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+ .clk_data = {
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+ [CLK_37_125] = imx290_37_125mhz_clock_1080p,
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+ [CLK_74_25] = imx290_74_250mhz_clock_1080p,
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+ },
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+ .clk_size = ARRAY_SIZE(imx290_37_125mhz_clock_1080p),
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},
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};
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@@ -331,6 +387,11 @@ static const struct imx290_mode imx290_m
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.link_freq_index = FREQ_INDEX_1080P,
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.data = imx290_1080p_settings,
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.data_size = ARRAY_SIZE(imx290_1080p_settings),
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+ .clk_data = {
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+ [CLK_37_125] = imx290_37_125mhz_clock_720p,
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+ [CLK_74_25] = imx290_74_250mhz_clock_720p,
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+ },
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+ .clk_size = ARRAY_SIZE(imx290_37_125mhz_clock_720p),
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},
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{
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.width = 1280,
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@@ -339,6 +400,11 @@ static const struct imx290_mode imx290_m
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.link_freq_index = FREQ_INDEX_720P,
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.data = imx290_720p_settings,
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.data_size = ARRAY_SIZE(imx290_720p_settings),
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+ .clk_data = {
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+ [CLK_37_125] = imx290_37_125mhz_clock_720p,
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+ [CLK_74_25] = imx290_74_250mhz_clock_720p,
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+ },
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+ .clk_size = ARRAY_SIZE(imx290_37_125mhz_clock_720p),
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},
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};
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@@ -712,6 +778,8 @@ static int imx290_set_hmax(struct imx290
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/* Start streaming */
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static int imx290_start_streaming(struct imx290 *imx290)
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{
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+ enum imx290_clk_index clk_idx = imx290->xclk_freq == 37125000 ?
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+ CLK_37_125 : CLK_74_25;
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int ret;
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/* Set init register settings */
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@@ -723,6 +791,14 @@ static int imx290_start_streaming(struct
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return ret;
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}
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+ ret = imx290_set_register_array(imx290,
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+ imx290->current_mode->clk_data[clk_idx],
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+ imx290->current_mode->clk_size);
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+ if (ret < 0) {
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+ dev_err(imx290->dev, "Could not set clock registers\n");
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+ return ret;
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+ }
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+
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/* Apply the register values related to current frame format */
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ret = imx290_write_current_format(imx290);
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if (ret < 0) {
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@@ -939,7 +1015,6 @@ static int imx290_probe(struct i2c_clien
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.bus_type = V4L2_MBUS_CSI2_DPHY
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};
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struct imx290 *imx290;
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- u32 xclk_freq;
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s64 fq;
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int ret;
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@@ -1003,21 +1078,21 @@ static int imx290_probe(struct i2c_clien
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}
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ret = fwnode_property_read_u32(dev_fwnode(dev), "clock-frequency",
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- &xclk_freq);
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+ &imx290->xclk_freq);
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if (ret) {
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dev_err(dev, "Could not get xclk frequency\n");
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goto free_err;
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}
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/* external clock must be 37.125 MHz */
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- if (xclk_freq != 37125000) {
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+ if (imx290->xclk_freq != 37125000 && imx290->xclk_freq != 74250000) {
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dev_err(dev, "External clock frequency %u is not supported\n",
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- xclk_freq);
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+ imx290->xclk_freq);
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ret = -EINVAL;
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goto free_err;
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}
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- ret = clk_set_rate(imx290->xclk, xclk_freq);
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+ ret = clk_set_rate(imx290->xclk, imx290->xclk_freq);
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if (ret) {
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dev_err(dev, "Could not set xclk frequency\n");
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goto free_err;
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