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62b7f5931c
bcm2708: boot tested on RPi B+ v1.2
bcm2709: boot tested on RPi 3B v1.2 and RPi 4B v1.1 4G
bcm2710: boot tested on RPi 3B v1.2
bcm2711: boot tested on RPi 4B v1.1 4G
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
(cherry-picked from commit f07e572f64)
87 lines
3.2 KiB
Diff
87 lines
3.2 KiB
Diff
From b8714036be64c86a274ea49ba0066af0a81c6b98 Mon Sep 17 00:00:00 2001
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From: Maxime Ripard <maxime@cerno.tech>
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Date: Thu, 26 Dec 2019 11:36:50 +0100
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Subject: [PATCH] drm/vc4: crtc: Deal with different number of pixel
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per clock
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Some of the HDMI pixelvalves in vc5 output two pixels per clock cycle.
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Let's put the number of pixel output per clock cycle in the CRTC data and
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update the various calculations to reflect that.
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Signed-off-by: Maxime Ripard <maxime@cerno.tech>
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---
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drivers/gpu/drm/vc4/vc4_crtc.c | 17 ++++++++++-------
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drivers/gpu/drm/vc4/vc4_drv.h | 3 +++
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2 files changed, 13 insertions(+), 7 deletions(-)
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--- a/drivers/gpu/drm/vc4/vc4_crtc.c
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+++ b/drivers/gpu/drm/vc4/vc4_crtc.c
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@@ -281,6 +281,7 @@ static void vc4_crtc_config_pv(struct dr
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bool is_dsi = (vc4_encoder->type == VC4_ENCODER_TYPE_DSI0 ||
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vc4_encoder->type == VC4_ENCODER_TYPE_DSI1);
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u32 format = is_dsi ? PV_CONTROL_FORMAT_DSIV_24 : PV_CONTROL_FORMAT_24;
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+ u8 ppc = vc4_crtc->data->pixels_per_clock;
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/* Reset the PV fifo. */
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CRTC_WRITE(PV_CONTROL, 0);
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@@ -288,17 +289,16 @@ static void vc4_crtc_config_pv(struct dr
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CRTC_WRITE(PV_CONTROL, 0);
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CRTC_WRITE(PV_HORZA,
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- VC4_SET_FIELD((mode->htotal -
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- mode->hsync_end) * pixel_rep,
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+ VC4_SET_FIELD((mode->htotal - mode->hsync_end) * pixel_rep / ppc,
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PV_HORZA_HBP) |
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- VC4_SET_FIELD((mode->hsync_end -
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- mode->hsync_start) * pixel_rep,
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+ VC4_SET_FIELD((mode->hsync_end - mode->hsync_start) * pixel_rep / ppc,
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PV_HORZA_HSYNC));
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+
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CRTC_WRITE(PV_HORZB,
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- VC4_SET_FIELD((mode->hsync_start -
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- mode->hdisplay) * pixel_rep,
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+ VC4_SET_FIELD((mode->hsync_start - mode->hdisplay) * pixel_rep / ppc,
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PV_HORZB_HFP) |
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- VC4_SET_FIELD(mode->hdisplay * pixel_rep, PV_HORZB_HACTIVE));
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+ VC4_SET_FIELD(mode->hdisplay * pixel_rep / ppc,
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+ PV_HORZB_HACTIVE));
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CRTC_WRITE(PV_VERTA,
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VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
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@@ -1038,6 +1038,7 @@ static const struct drm_crtc_helper_func
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static const struct vc4_crtc_data bcm2835_pv0_data = {
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.hvs_channel = 0,
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.debugfs_name = "crtc0_regs",
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+ .pixels_per_clock = 1,
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.encoder_types = {
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[PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI0,
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[PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_DPI,
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@@ -1047,6 +1048,7 @@ static const struct vc4_crtc_data bcm283
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static const struct vc4_crtc_data bcm2835_pv1_data = {
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.hvs_channel = 2,
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.debugfs_name = "crtc1_regs",
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+ .pixels_per_clock = 1,
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.encoder_types = {
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[PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI1,
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[PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_SMI,
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@@ -1056,6 +1058,7 @@ static const struct vc4_crtc_data bcm283
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static const struct vc4_crtc_data bcm2835_pv2_data = {
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.hvs_channel = 1,
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.debugfs_name = "crtc2_regs",
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+ .pixels_per_clock = 1,
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.encoder_types = {
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[PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_HDMI,
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[PV_CONTROL_CLK_SELECT_VEC] = VC4_ENCODER_TYPE_VEC,
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--- a/drivers/gpu/drm/vc4/vc4_drv.h
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+++ b/drivers/gpu/drm/vc4/vc4_drv.h
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@@ -455,6 +455,9 @@ struct vc4_crtc_data {
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/* Which channel of the HVS this pixelvalve sources from. */
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int hvs_channel;
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+ /* Number of pixels output per clock period */
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+ u8 pixels_per_clock;
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+
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enum vc4_encoder_type encoder_types[4];
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const char *debugfs_name;
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};
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