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62b7f5931c
bcm2708: boot tested on RPi B+ v1.2
bcm2709: boot tested on RPi 3B v1.2 and RPi 4B v1.1 4G
bcm2710: boot tested on RPi 3B v1.2
bcm2711: boot tested on RPi 4B v1.1 4G
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
(cherry-picked from commit f07e572f64)
50 lines
1.8 KiB
Diff
50 lines
1.8 KiB
Diff
From edbbc60ed86f4b690838e6c4b0aed48803e334cc Mon Sep 17 00:00:00 2001
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From: Jonathan Bell <jonathan@raspberrypi.org>
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Date: Mon, 13 Jan 2020 15:54:55 +0000
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Subject: [PATCH] dwc_otg: fiq_fsm: add a barrier on entry into FIQ
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handler(s)
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On BCM2835, there is no hardware guarantee that multiple outstanding
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reads to different peripherals will complete in-order. The FIQ code
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uses peripheral reads without barriers for performance, so in the case
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where a read to a slow peripheral was issued immediately prior to FIQ
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entry, the first peripheral read that the FIQ did could end up with
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wrong read data returned.
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Add dsb(sy) on entry so that all outstanding reads are retired.
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The FIQ only issues reads to the dwc_otg core, so per-read barriers
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in the handler itself are not required.
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On BCM2836 and BCM2837 the barrier is not strictly required due to
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differences in how the peripheral bus is implemented, but having
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arch-specific handlers that introduce different latencies is risky.
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Signed-off-by: Jonathan Bell <jonathan@raspberrypi.org>
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---
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drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c | 6 ++++++
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1 file changed, 6 insertions(+)
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--- a/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c
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+++ b/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c
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@@ -1259,6 +1259,9 @@ void notrace dwc_otg_fiq_fsm(struct fiq_
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haintmsk_data_t haintmsk;
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int kick_irq = 0;
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+ /* Ensure peripheral reads issued prior to FIQ entry are complete */
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+ dsb(sy);
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+
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gintsts_handled.d32 = 0;
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haint_handled.d32 = 0;
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@@ -1379,6 +1382,9 @@ void notrace dwc_otg_fiq_nop(struct fiq_
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gintmsk_data_t gintmsk;
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hfnum_data_t hfnum;
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+ /* Ensure peripheral reads issued prior to FIQ entry are complete */
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+ dsb(sy);
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+
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fiq_fsm_spin_lock(&state->lock);
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hfnum.d32 = FIQ_READ(state->dwc_regs_base + HFNUM);
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gintsts.d32 = FIQ_READ(state->dwc_regs_base + GINTSTS);
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