openwrt/target/linux/bcm27xx/patches-5.10/950-0511-vc4-drm-Fix-source-offsets-with-DRM_FORMAT_P030.patch
John Audia 24d84a13a4 kernel: bump 5.10 to 5.10.173
Manually rebased:
        ramips/patches-5.10/810-uvc-add-iPassion-iP2970-support.patch

All other patches automatically rebased.

Signed-off-by: John Audia <therealgraysky@proton.me>
(cherry picked from commit d4aad642ff)
2023-03-27 18:58:34 +02:00

72 lines
2.4 KiB
Diff

From c470db2240fa76293025852533ae8bf1c5679bfb Mon Sep 17 00:00:00 2001
From: Dom Cobley <popcornmix@gmail.com>
Date: Mon, 22 Mar 2021 19:43:48 +0000
Subject: [PATCH] vc4/drm: Fix source offsets with DRM_FORMAT_P030
Spec says: bits [31:4] of the given address should point to
the 128-bit word containing the desired starting pixel,
and bits[3:0] should be between 0 and 11, indicating which
of the 12-pixels in that 128-bit word is the first pixel to be used
Signed-off-by: Dom Cobley <popcornmix@gmail.com>
---
drivers/gpu/drm/vc4/vc4_plane.c | 24 ++++++++++++++++--------
1 file changed, 16 insertions(+), 8 deletions(-)
--- a/drivers/gpu/drm/vc4/vc4_plane.c
+++ b/drivers/gpu/drm/vc4/vc4_plane.c
@@ -822,9 +822,20 @@ static int vc4_plane_mode_set(struct drm
u32 tile_w, tile, x_off, pix_per_tile;
if (fb->format->format == DRM_FORMAT_P030) {
+ /*
+ * Spec says: bits [31:4] of the given address should point to
+ * the 128-bit word containing the desired starting pixel,
+ * and bits[3:0] should be between 0 and 11, indicating which
+ * of the 12-pixels in that 128-bit word is the first pixel to be used
+ */
+ u32 aligned = vc4_state->src_x / 12;
+ u32 last_bits = vc4_state->src_x % 12;
+
+ x_off = aligned * 16 + last_bits;
hvs_format = HVS_PIXEL_FORMAT_YCBCR_10BIT;
tiling = SCALER_CTL0_TILING_128B;
- tile_w = 96;
+ tile_w = 128;
+ pix_per_tile = 96;
} else {
hvs_format = HVS_PIXEL_FORMAT_H264;
@@ -844,17 +855,16 @@ static int vc4_plane_mode_set(struct drm
default:
break;
}
+ pix_per_tile = tile_w / fb->format->cpp[0];
+ x_off = (vc4_state->src_x % pix_per_tile) /
+ (i ? h_subsample : 1) * fb->format->cpp[i];
}
if (param > SCALER_TILE_HEIGHT_MASK) {
DRM_DEBUG_KMS("SAND height too large (%d)\n",
param);
return -EINVAL;
}
-
- pix_per_tile = tile_w / fb->format->cpp[0];
tile = vc4_state->src_x / pix_per_tile;
- x_off = vc4_state->src_x % pix_per_tile;
-
/* Adjust the base pointer to the first pixel to be scanned
* out.
*
@@ -870,9 +880,7 @@ static int vc4_plane_mode_set(struct drm
vc4_state->offsets[i] += src_y /
(i ? v_subsample : 1) *
tile_w;
- vc4_state->offsets[i] += x_off /
- (i ? h_subsample : 1) *
- fb->format->cpp[i];
+ vc4_state->offsets[i] += x_off & ~(i ? 1 : 0);
}
pitch0 = VC4_SET_FIELD(param, SCALER_TILE_HEIGHT);