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e58cd453d5
Add kernel support for SAMA7G5 by back-porting mainline kernel patches. Among SAMA7G5 features could be remembered: - ARM Cortex-A7 - double data rate multi-port dynamic RAM controller supporting DDR2, DDR3, DDR3L, LPDDR2, LPDDR3 up to 533MHz - peripherals for audio, video processing - 1 gigabit + 1 megabit Ethernet controllers - 6 CAN controllers - trust zone support - DVFS for CPU - criptography IPs Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
156 lines
3.4 KiB
Diff
156 lines
3.4 KiB
Diff
From 67face049c62cb37cf93da26b7fea037228d1d3d Mon Sep 17 00:00:00 2001
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From: Claudiu Beznea <claudiu.beznea@microchip.com>
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Date: Thu, 15 Apr 2021 13:49:55 +0300
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Subject: [PATCH 205/247] ARM: at91: pm: add support for waiting MCK1..4
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SAMA7G5 has 5 master clocks 0..4. MCK0 is controlled differently than
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MCK 1..4. MCK 1..4 should also be saved/restored in the last phase of
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suspend/resume. Thus, adapt wait_mckrdy to support also MCK1..4.
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Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
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Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
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Link: https://lore.kernel.org/r/20210415105010.569620-10-claudiu.beznea@microchip.com
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---
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arch/arm/mach-at91/pm_suspend.S | 48 ++++++++++++++++++++++++---------
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1 file changed, 35 insertions(+), 13 deletions(-)
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diff --git a/arch/arm/mach-at91/pm_suspend.S b/arch/arm/mach-at91/pm_suspend.S
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index 1f63bbfad728..7669b32d5257 100644
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--- a/arch/arm/mach-at91/pm_suspend.S
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+++ b/arch/arm/mach-at91/pm_suspend.S
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@@ -22,11 +22,23 @@ tmp3 .req r6
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/*
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* Wait until master clock is ready (after switching master clock source)
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+ *
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+ * @r_mckid: register holding master clock identifier
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+ *
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+ * Side effects: overwrites r7, r8
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*/
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- .macro wait_mckrdy
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-1: ldr tmp1, [pmc, #AT91_PMC_SR]
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- tst tmp1, #AT91_PMC_MCKRDY
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- beq 1b
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+ .macro wait_mckrdy r_mckid
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+#ifdef CONFIG_SOC_SAMA7
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+ cmp \r_mckid, #0
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+ beq 1f
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+ mov r7, #AT91_PMC_MCKXRDY
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+ b 2f
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+#endif
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+1: mov r7, #AT91_PMC_MCKRDY
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+2: ldr r8, [pmc, #AT91_PMC_SR]
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+ and r8, r7
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+ cmp r8, r7
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+ bne 2b
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.endm
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/*
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@@ -231,7 +243,9 @@ sr_dis_exit:
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bic tmp1, tmp1, #AT91_PMC_PRES
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orr tmp1, tmp1, #AT91_PMC_PRES_64
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str tmp1, [pmc, tmp3]
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- wait_mckrdy
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+
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+ mov tmp3, #0
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+ wait_mckrdy tmp3
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b 1f
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0:
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@@ -267,10 +281,13 @@ sr_dis_exit:
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bne 5f
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/* Set lowest prescaler for fast resume. */
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+ ldr tmp3, .mckr_offset
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ldr tmp1, [pmc, tmp3]
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bic tmp1, tmp1, #AT91_PMC_PRES
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str tmp1, [pmc, tmp3]
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- wait_mckrdy
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+
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+ mov tmp3, #0
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+ wait_mckrdy tmp3
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b 6f
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5: /* Restore RC oscillator state */
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@@ -307,6 +324,7 @@ sr_dis_exit:
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.macro at91_pm_ulp1_mode
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ldr pmc, .pmc_base
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ldr tmp2, .mckr_offset
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+ mov tmp3, #0
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/* Save RC oscillator state and check if it is enabled. */
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ldr tmp1, [pmc, #AT91_PMC_SR]
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@@ -348,7 +366,7 @@ sr_dis_exit:
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orr tmp1, tmp1, #AT91_PMC_CSS_MAIN
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str tmp1, [pmc, tmp2]
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- wait_mckrdy
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+ wait_mckrdy tmp3
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/* Enter the ULP1 mode by set WAITMODE bit in CKGR_MOR */
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ldr tmp1, [pmc, #AT91_CKGR_MOR]
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@@ -361,7 +379,7 @@ sr_dis_exit:
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nop
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nop
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- wait_mckrdy
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+ wait_mckrdy tmp3
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/* Enable the crystal oscillator */
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ldr tmp1, [pmc, #AT91_CKGR_MOR]
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@@ -377,7 +395,7 @@ sr_dis_exit:
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bic tmp1, tmp1, #AT91_PMC_CSS
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str tmp1, [pmc, tmp2]
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- wait_mckrdy
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+ wait_mckrdy tmp3
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/* Switch main clock source to crystal oscillator */
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ldr tmp1, [pmc, #AT91_CKGR_MOR]
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@@ -394,7 +412,7 @@ sr_dis_exit:
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orr tmp1, tmp1, #AT91_PMC_CSS_MAIN
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str tmp1, [pmc, tmp2]
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- wait_mckrdy
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+ wait_mckrdy tmp3
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/* Restore RC oscillator state */
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ldr tmp1, .saved_osc_status
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@@ -573,10 +591,12 @@ sr_dis_exit:
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save_mck:
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str tmp1, [pmc, tmp2]
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- wait_mckrdy
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+ mov tmp3, #0
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+ wait_mckrdy tmp3
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at91_plla_disable
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+ ldr tmp3, .pm_mode
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cmp tmp3, #AT91_PM_ULP1
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beq ulp1_mode
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@@ -599,7 +619,8 @@ ulp_exit:
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ldr tmp2, .saved_mckr
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str tmp2, [pmc, tmp1]
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- wait_mckrdy
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+ mov tmp3, #0
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+ wait_mckrdy tmp3
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.endm
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@@ -611,7 +632,8 @@ ulp_exit:
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bic tmp1, tmp1, #AT91_PMC_CSS
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str tmp1, [pmc, tmp2]
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- wait_mckrdy
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+ mov tmp3, #0
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+ wait_mckrdy tmp3
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/*BUMEN*/
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ldr r0, .sfrbu
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--
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2.32.0
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