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f02f6aaa8d
Currently, ipq807x only covers Qualcomm IPQ807x SoC-s. However, Qualcomm also has IPQ60xx and IPQ50xx SoC-s under the AX WiSoC-s and they share a lot of stuff with IPQ807x, especially IPQ60xx so to avoid duplicating kernel patches and everything lets make a common target with per SoC subtargets. Start doing that by renaming ipq807x to qualcommax so that dependencies on ipq807x target can be updated. Signed-off-by: Robert Marko <robimarko@gmail.com>
61 lines
1.8 KiB
Diff
61 lines
1.8 KiB
Diff
From 5f20690f77878b1ba24ec88df01b92d5131a6780 Mon Sep 17 00:00:00 2001
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From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Date: Tue, 8 Nov 2022 15:23:57 +0100
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Subject: [PATCH] arm64: dts: qcom: ipq8074: align TLMM pin configuration with
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DT schema
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DT schema expects TLMM pin configuration nodes to be named with
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'-state' suffix and their optional children with '-pins' suffix.
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Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
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Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Link: https://lore.kernel.org/r/20221108142357.67202-2-krzysztof.kozlowski@linaro.org
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---
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arch/arm64/boot/dts/qcom/ipq8074.dtsi | 10 +++++-----
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1 file changed, 5 insertions(+), 5 deletions(-)
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--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
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@@ -318,35 +318,35 @@
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interrupt-controller;
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#interrupt-cells = <0x2>;
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- serial_4_pins: serial4-pinmux {
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+ serial_4_pins: serial4-state {
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pins = "gpio23", "gpio24";
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function = "blsp4_uart1";
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drive-strength = <8>;
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bias-disable;
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};
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- i2c_0_pins: i2c-0-pinmux {
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+ i2c_0_pins: i2c-0-state {
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pins = "gpio42", "gpio43";
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function = "blsp1_i2c";
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drive-strength = <8>;
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bias-disable;
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};
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- spi_0_pins: spi-0-pins {
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+ spi_0_pins: spi-0-state {
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pins = "gpio38", "gpio39", "gpio40", "gpio41";
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function = "blsp0_spi";
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drive-strength = <8>;
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bias-disable;
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};
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- hsuart_pins: hsuart-pins {
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+ hsuart_pins: hsuart-state {
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pins = "gpio46", "gpio47", "gpio48", "gpio49";
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function = "blsp2_uart";
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drive-strength = <8>;
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bias-disable;
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};
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- qpic_pins: qpic-pins {
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+ qpic_pins: qpic-state {
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pins = "gpio1", "gpio3", "gpio4",
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"gpio5", "gpio6", "gpio7",
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"gpio8", "gpio10", "gpio11",
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