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e3559fb445
Changelog: https://cdn.kernel.org/pub/linux/kernel/v6.x/ChangeLog-6.1.54 Removed upstreamed: generic/backport-6.1/020-v6.3-02-UPSTREAM-mm-multi-gen-LRU-rename-lrugen-lists-to-lru.patch[1] ipq806x/patches-6.1/140-v6.5-hwspinlock-qcom-add-missing-regmap-config-for-SFPB-M.patch[2] All other patches automatically rebased. 1. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.1.54&id=a73d04c460521e45f257d28d73df096e41ece324 2. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.1.54&id=e93bc372dbc0bde133c854c03502a95617041972 Build system: x86/64 Build-tested: x86/64/AMD Cezanne Run-tested: x86/64/AMD Cezanne Signed-off-by: John Audia <therealgraysky@proton.me>
79 lines
2.8 KiB
Diff
79 lines
2.8 KiB
Diff
From 5b71dbb867680887d47954ce1cc145cb747cbce6 Mon Sep 17 00:00:00 2001
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From: Maxime Chevallier <maxime.chevallier@bootlin.com>
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Date: Fri, 4 Nov 2022 18:41:51 +0100
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Subject: [PATCH] ARM: dts: qcom: ipq4019: Add description for the IPQESS
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Ethernet controller
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The Qualcomm IPQ4019 includes an internal 5 ports switch, which is
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connected to the CPU through the internal IPQESS Ethernet controller.
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Add support for this internal interface, which is internally connected to a
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modified version of the QCA8K Ethernet switch.
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This Ethernet controller only support a specific internal interface mode
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for connection to the switch.
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Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
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Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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---
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arch/arm/boot/dts/qcom-ipq4019.dtsi | 48 +++++++++++++++++++++++++++++
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1 file changed, 48 insertions(+)
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--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
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+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
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@@ -594,6 +594,54 @@
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status = "disabled";
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};
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+ gmac: ethernet@c080000 {
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+ compatible = "qcom,ipq4019-ess-edma";
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+ reg = <0xc080000 0x8000>;
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+ resets = <&gcc ESS_RESET>;
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+ reset-names = "ess";
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+ clocks = <&gcc GCC_ESS_CLK>;
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+ clock-names = "ess";
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+ interrupts = <GIC_SPI 65 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 66 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 67 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 69 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 71 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 76 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 77 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 240 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 241 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 242 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 243 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 244 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 245 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 246 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 247 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 248 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 249 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 250 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 251 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 252 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 253 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 254 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 255 IRQ_TYPE_EDGE_RISING>;
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+ phy-mode = "internal";
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+ status = "disabled";
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+ fixed-link {
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+ speed = <1000>;
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+ full-duplex;
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+ pause;
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+ };
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+ };
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+
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mdio: mdio@90000 {
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#address-cells = <1>;
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#size-cells = <0>;
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