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99545b4bb1
This target adds support for the Allwinner D1 RISC-V based SoCs.
- RISC-V single-core T-Head C906 (RV64GCV)
- Tensilica HiFi4 DSP
- DDR2/DDR3 support
- 10/100/1000M ethernet
- usual peripherals like USB2, SPI, I2C, PWM, etc.
Four boards are supported:
- Dongshan Nezha STU
- 512Mb RAM
- ethernet
- LicheePi RV Dock
- 512Mb RAM
- wireless-only (RTL8723DS)
- MangoPi MQ-Pro
- 512Mb RAM
- there are pads available for an SPI flash
- wireless-only (RTL8723DS)
- Nezha D1
- 512Mb/1Gb/2Gb RAM
- 256Mb NAND flash
- ethernet, wireless
Installation:
Standard SD-card installation via dd-ing the generated image to
an SD-card of at least 256Mb.
Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
68 lines
3.4 KiB
Diff
68 lines
3.4 KiB
Diff
From 02da00f2215f3d755ec806636fe499331870e8d6 Mon Sep 17 00:00:00 2001
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From: Samuel Holland <samuel@sholland.org>
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Date: Tue, 9 Aug 2022 20:14:59 -0500
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Subject: [PATCH 114/117] drm: panel: cwd686: Use the init sequence from the
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R-01 BSP
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Signed-off-by: Samuel Holland <samuel@sholland.org>
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---
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.../gpu/drm/panel/panel-clockwork-cwd686.c | 44 ++++++++-----------
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1 file changed, 19 insertions(+), 25 deletions(-)
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--- a/drivers/gpu/drm/panel/panel-clockwork-cwd686.c
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+++ b/drivers/gpu/drm/panel/panel-clockwork-cwd686.c
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@@ -131,34 +131,28 @@ static int cwd686_init_sequence(struct c
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{
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struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
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- dcs_write_seq(0xF0,0x5A,0x5A);
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- dcs_write_seq(0xF1,0xA5,0xA5);
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- dcs_write_seq(0xB6,0x0D,0x0D);
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- dcs_write_seq(0xB4,0x0A,0x08,0x12,0x10,0x0E,0x0C,0x00,0x00,0x00,0x03,0x00,0x03,0x03,0x03,0x03,0x03,0x03,0x03,0x04,0x06);
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- dcs_write_seq(0xB3,0x0B,0x09,0x13,0x11,0x0F,0x0D,0x00,0x00,0x00,0x03,0x00,0x03,0x03,0x03,0x03,0x03,0x03,0x03,0x05,0x07);
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- dcs_write_seq(0xB0,0x54,0x32,0x23,0x45,0x44,0x44,0x44,0x44,0x90,0x01,0x90,0x01);
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- dcs_write_seq(0xB1,0x32,0x84,0x02,0x83,0x30,0x01,0x6B,0x01);
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+ dcs_write_seq(0xF0,0x5A,0x59);
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+ dcs_write_seq(0xF1,0xA5,0xA6);
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+ dcs_write_seq(0xB0,0x54,0x32,0x23,0x45,0x44,0x44,0x44,0x44,0x9F,0x00,0x01,0x9F,0x00,0x01);
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+ dcs_write_seq(0xB1,0x32,0x84,0x02,0x83,0x29,0x06,0x06,0x72,0x06,0x06);
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dcs_write_seq(0xB2,0x73);
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- dcs_write_seq(0xBD,0x4E,0x0E,0x50,0x50,0x26,0x1D,0x00,0x14,0x42,0x03);
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- dcs_write_seq(0xB7,0x01,0x01,0x09,0x11,0x0D,0x55,0x19,0x19,0x21,0x1D,0x00,0x00,0x00,0x00,0x02,0xFF,0x3C);
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- dcs_write_seq(0xB8,0x23,0x01,0x30,0x34,0x63);
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- dcs_write_seq(0xB9,0xA0,0x22,0x00,0x44);
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- dcs_write_seq(0xBA,0x12,0x63);
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- dcs_write_seq(0xC1,0x0C,0x16,0x04,0x0C,0x10,0x04);
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- dcs_write_seq(0xC2,0x11,0x41);
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- dcs_write_seq(0xC3,0x22,0x31,0x04);
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- dcs_write_seq(0xC7,0x05,0x23,0x6B,0x49,0x00);
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- dcs_write_seq(0xC5,0x00);
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- dcs_write_seq(0xD0,0x37,0xFF,0xFF);
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- dcs_write_seq(0xD2,0x63,0x0B,0x08,0x88);
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- dcs_write_seq(0xD3,0x01,0x00,0x00,0x01,0x01,0x37,0x25,0x38,0x31,0x06,0x07);
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- dcs_write_seq(0xC8,0x7C,0x6A,0x5D,0x53,0x53,0x45,0x4B,0x35,0x4D,0x4A,0x49,0x66,0x53,0x57,0x4A,0x48,0x3B,0x2A,0x06,0x7C,0x6A,0x5D,0x53,0x53,0x45,0x4B,0x35,0x4D,0x4A,0x49,0x66,0x53,0x57,0x4A,0x48,0x3B,0x2A,0x06);//GAMMA2.2
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- dcs_write_seq(0xC6,0x00,0x00,0xFF,0x00,0x00,0xFF,0x00,0x00);
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- dcs_write_seq(0xF4,0x08,0x77);
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+ dcs_write_seq(0xB3,0x0B,0x09,0x13,0x11,0x0F,0x0D,0x00,0x00,0x00,0x03,0x00,0x03,0x03,0x03,0x03,0x03,0x03,0x03,0x05,0x07);
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+ dcs_write_seq(0xB4,0x0A,0x08,0x12,0x10,0x0E,0x0C,0x00,0x00,0x00,0x03,0x00,0x03,0x03,0x03,0x03,0x03,0x03,0x03,0x04,0x06);
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+ dcs_write_seq(0xB6,0x13,0x13);
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+ dcs_write_seq(0xB8,0xB4,0x43,0x02,0xCC);
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+ dcs_write_seq(0xB9,0xA5,0x20,0xFF,0xC8);
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+ dcs_write_seq(0xBA,0x88,0x23);
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+ dcs_write_seq(0xBD,0x43,0x0E,0x0E,0x50,0x50,0x29,0x10,0x03,0x44,0x03);
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+ dcs_write_seq(0xC1,0x00,0x0C,0x16,0x04,0x00,0x30,0x10,0x04);
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+ dcs_write_seq(0xC2,0x21,0x81);
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+ dcs_write_seq(0xC3,0x02,0x30);
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+ dcs_write_seq(0xC7,0x25,0x6A);
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+ dcs_write_seq(0xC8,0x7C,0x68,0x59,0x4E,0x4B,0x3C,0x41,0x2B,0x44,0x43,0x43,0x60,0x4E,0x55,0x47,0x44,0x38,0x27,0x06,0x7C,0x68,0x59,0x4E,0x4B,0x3C,0x41,0x2B,0x44,0x43,0x43,0x60,0x4E,0x55,0x47,0x44,0x38,0x27,0x06);
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+ dcs_write_seq(0xD4,0x00,0x00,0x00,0x32,0x04,0x51);
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+ dcs_write_seq(0xF1,0x5A,0x59);
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+ dcs_write_seq(0xF0,0xA5,0xA6);
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dcs_write_seq(0x36,0x14);
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dcs_write_seq(0x35,0x00);
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- dcs_write_seq(0xF1,0x5A,0x5A);
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- dcs_write_seq(0xF0,0xA5,0xA5);
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return 0;
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}
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