mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-25 16:31:13 +00:00
34 lines
1.5 KiB
Diff
34 lines
1.5 KiB
Diff
From 4f0328557a670d481f2609474b56890c28ab4694 Mon Sep 17 00:00:00 2001
|
|
From: Matthew McClintock <mmcclint@qca.qualcomm.com>
|
|
Date: Thu, 28 Apr 2016 12:55:08 -0500
|
|
Subject: [PATCH 27/37] clk: ipq4019: report accurate fixed clock rates
|
|
|
|
This looks like a copy-and-paste gone wrong, but update all
|
|
the fixed clock rates to report the correct values.
|
|
|
|
Signed-off-by: Matthew McClintock <mmcclint@qca.qualcomm.com>
|
|
---
|
|
drivers/clk/qcom/gcc-ipq4019.c | 10 +++++-----
|
|
1 file changed, 5 insertions(+), 5 deletions(-)
|
|
|
|
--- a/drivers/clk/qcom/gcc-ipq4019.c
|
|
+++ b/drivers/clk/qcom/gcc-ipq4019.c
|
|
@@ -1317,12 +1317,12 @@ static int gcc_ipq4019_probe(struct plat
|
|
{
|
|
struct device *dev = &pdev->dev;
|
|
|
|
- clk_register_fixed_rate(dev, "fepll125", "xo", 0, 200000000);
|
|
- clk_register_fixed_rate(dev, "fepll125dly", "xo", 0, 200000000);
|
|
- clk_register_fixed_rate(dev, "fepllwcss2g", "xo", 0, 200000000);
|
|
- clk_register_fixed_rate(dev, "fepllwcss5g", "xo", 0, 200000000);
|
|
+ clk_register_fixed_rate(dev, "fepll125", "xo", 0, 125000000);
|
|
+ clk_register_fixed_rate(dev, "fepll125dly", "xo", 0, 125000000);
|
|
+ clk_register_fixed_rate(dev, "fepllwcss2g", "xo", 0, 250000000);
|
|
+ clk_register_fixed_rate(dev, "fepllwcss5g", "xo", 0, 250000000);
|
|
clk_register_fixed_rate(dev, "fepll200", "xo", 0, 200000000);
|
|
- clk_register_fixed_rate(dev, "fepll500", "xo", 0, 200000000);
|
|
+ clk_register_fixed_rate(dev, "fepll500", "xo", 0, 500000000);
|
|
clk_register_fixed_rate(dev, "ddrpllapss", "xo", 0, 666000000);
|
|
|
|
return qcom_cc_probe(pdev, &gcc_ipq4019_desc);
|