mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-24 15:56:49 +00:00
125 lines
3.4 KiB
Diff
125 lines
3.4 KiB
Diff
From bf5cb424312f28e51803286a53cb8613bedc5bc8 Mon Sep 17 00:00:00 2001
|
|
From: Gabor Juhos <juhosg@openwrt.org>
|
|
Date: Wed, 14 Mar 2012 10:45:21 +0100
|
|
Subject: [PATCH 26/47] MIPS: ath79: add SoC detection code for AR934X
|
|
|
|
Also add 'soc_is_ar934[124x]' helper functions and a Kconfig
|
|
symbol for the AR934X SoCs.
|
|
|
|
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
|
|
Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
|
|
Cc: linux-mips@linux-mips.org
|
|
Cc: mcgrof@infradead.org
|
|
Patchwork: https://patchwork.linux-mips.org/patch/3506/
|
|
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
|
|
---
|
|
arch/mips/ath79/Kconfig | 4 ++++
|
|
arch/mips/ath79/setup.c | 21 ++++++++++++++++++++-
|
|
arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 2 ++
|
|
arch/mips/include/asm/mach-ath79/ath79.h | 23 +++++++++++++++++++++++
|
|
4 files changed, 49 insertions(+), 1 deletions(-)
|
|
|
|
--- a/arch/mips/ath79/Kconfig
|
|
+++ b/arch/mips/ath79/Kconfig
|
|
@@ -69,6 +69,10 @@ config SOC_AR933X
|
|
select USB_ARCH_HAS_EHCI
|
|
def_bool n
|
|
|
|
+config SOC_AR934X
|
|
+ select USB_ARCH_HAS_EHCI
|
|
+ def_bool n
|
|
+
|
|
config ATH79_DEV_GPIO_BUTTONS
|
|
def_bool n
|
|
|
|
--- a/arch/mips/ath79/setup.c
|
|
+++ b/arch/mips/ath79/setup.c
|
|
@@ -1,10 +1,11 @@
|
|
/*
|
|
* Atheros AR71XX/AR724X/AR913X specific setup
|
|
*
|
|
+ * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
|
|
* Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
|
|
* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
|
|
*
|
|
- * Parts of this file are based on Atheros' 2.6.15 BSP
|
|
+ * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify it
|
|
* under the terms of the GNU General Public License version 2 as published
|
|
@@ -145,6 +146,24 @@ static void __init ath79_detect_sys_type
|
|
rev = id & AR933X_REV_ID_REVISION_MASK;
|
|
break;
|
|
|
|
+ case REV_ID_MAJOR_AR9341:
|
|
+ ath79_soc = ATH79_SOC_AR9341;
|
|
+ chip = "9341";
|
|
+ rev = id & AR934X_REV_ID_REVISION_MASK;
|
|
+ break;
|
|
+
|
|
+ case REV_ID_MAJOR_AR9342:
|
|
+ ath79_soc = ATH79_SOC_AR9342;
|
|
+ chip = "9342";
|
|
+ rev = id & AR934X_REV_ID_REVISION_MASK;
|
|
+ break;
|
|
+
|
|
+ case REV_ID_MAJOR_AR9344:
|
|
+ ath79_soc = ATH79_SOC_AR9344;
|
|
+ chip = "9344";
|
|
+ rev = id & AR934X_REV_ID_REVISION_MASK;
|
|
+ break;
|
|
+
|
|
default:
|
|
panic("ath79: unknown SoC, id:0x%08x", id);
|
|
}
|
|
--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
|
|
+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
|
|
@@ -271,6 +271,8 @@
|
|
|
|
#define AR724X_REV_ID_REVISION_MASK 0x3
|
|
|
|
+#define AR934X_REV_ID_REVISION_MASK 0xf
|
|
+
|
|
/*
|
|
* SPI block
|
|
*/
|
|
--- a/arch/mips/include/asm/mach-ath79/ath79.h
|
|
+++ b/arch/mips/include/asm/mach-ath79/ath79.h
|
|
@@ -29,6 +29,9 @@ enum ath79_soc_type {
|
|
ATH79_SOC_AR9132,
|
|
ATH79_SOC_AR9330,
|
|
ATH79_SOC_AR9331,
|
|
+ ATH79_SOC_AR9341,
|
|
+ ATH79_SOC_AR9342,
|
|
+ ATH79_SOC_AR9344,
|
|
};
|
|
|
|
extern enum ath79_soc_type ath79_soc;
|
|
@@ -75,6 +78,26 @@ static inline int soc_is_ar933x(void)
|
|
ath79_soc == ATH79_SOC_AR9331);
|
|
}
|
|
|
|
+static inline int soc_is_ar9341(void)
|
|
+{
|
|
+ return (ath79_soc == ATH79_SOC_AR9341);
|
|
+}
|
|
+
|
|
+static inline int soc_is_ar9342(void)
|
|
+{
|
|
+ return (ath79_soc == ATH79_SOC_AR9342);
|
|
+}
|
|
+
|
|
+static inline int soc_is_ar9344(void)
|
|
+{
|
|
+ return (ath79_soc == ATH79_SOC_AR9344);
|
|
+}
|
|
+
|
|
+static inline int soc_is_ar934x(void)
|
|
+{
|
|
+ return soc_is_ar9341() || soc_is_ar9342() || soc_is_ar9344();
|
|
+}
|
|
+
|
|
extern void __iomem *ath79_ddr_base;
|
|
extern void __iomem *ath79_pll_base;
|
|
extern void __iomem *ath79_reset_base;
|