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Refresh all patches on top of kernel 5.10.138. The following patches were applied upstream: bcm27xx/patches-5.10/950-0311-drm-vc4-Adopt-the-dma-configuration-from-the-HVS-or-.patch bcm27xx/patches-5.10/950-0317-vc4_hdmi-Remove-firmware-logic-for-MAI-threshold-set.patch bcm27xx/patches-5.10/950-0346-drm-vc4-A-present-but-empty-dmas-disables-audio.patch bcm27xx/patches-5.10/950-0354-drm-vc4-Add-the-2711-HVS-as-a-suitable-DMA-node.patch bcm27xx/patches-5.10/950-0413-drm-vc4-hdmi-Don-t-access-the-connector-state-in-res.patch bcm27xx/patches-5.10/950-0505-vc4-drm-Avoid-full-hdmi-audio-fifo-writes.patch bcm27xx/patches-5.10/950-0512-vc4-drm-vc4_plane-Remove-subpixel-positioning-check.patch bcm27xx/patches-5.10/950-0560-drm-vc4-drv-Remove-the-DSI-pointer-in-vc4_drv.patch bcm27xx/patches-5.10/950-0561-drm-vc4-dsi-Use-snprintf-for-the-PHY-clocks-instead-.patch bcm27xx/patches-5.10/950-0562-drm-vc4-dsi-Introduce-a-variant-structure.patch bcm27xx/patches-5.10/950-0565-drm-vc4-Correct-pixel-order-for-DSI0.patch bcm27xx/patches-5.10/950-0566-drm-vc4-Register-dsi0-as-the-correct-vc4-encoder-typ.patch bcm27xx/patches-5.10/950-0567-drm-vc4-Fix-dsi0-interrupt-support.patch bcm27xx/patches-5.10/950-0568-drm-vc4-Add-correct-stop-condition-to-vc4_dsi_encode.patch bcm27xx/patches-5.10/950-0647-drm-vc4-Fix-timings-for-interlaced-modes.patch bcm27xx/patches-5.10/950-0695-drm-vc4-Fix-margin-calculations-for-the-right-bottom.patch Upstream sets the pixel clock to 340MHz now, do not set it to 600MHz any more. bcm27xx/patches-5.10/950-0576-drm-vc4-hdmi-Raise-the-maximum-clock-rate.patch Fixes:89956c6532("kernel: bump 5.10 to 5.10.138") Fixes:4209c33ae2("kernel: bump 5.10 to 5.10.137") Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
72 lines
2.4 KiB
Diff
72 lines
2.4 KiB
Diff
From c470db2240fa76293025852533ae8bf1c5679bfb Mon Sep 17 00:00:00 2001
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From: Dom Cobley <popcornmix@gmail.com>
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Date: Mon, 22 Mar 2021 19:43:48 +0000
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Subject: [PATCH] vc4/drm: Fix source offsets with DRM_FORMAT_P030
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Spec says: bits [31:4] of the given address should point to
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the 128-bit word containing the desired starting pixel,
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and bits[3:0] should be between 0 and 11, indicating which
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of the 12-pixels in that 128-bit word is the first pixel to be used
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Signed-off-by: Dom Cobley <popcornmix@gmail.com>
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---
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drivers/gpu/drm/vc4/vc4_plane.c | 24 ++++++++++++++++--------
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1 file changed, 16 insertions(+), 8 deletions(-)
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--- a/drivers/gpu/drm/vc4/vc4_plane.c
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+++ b/drivers/gpu/drm/vc4/vc4_plane.c
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@@ -820,9 +820,20 @@ static int vc4_plane_mode_set(struct drm
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u32 tile_w, tile, x_off, pix_per_tile;
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if (fb->format->format == DRM_FORMAT_P030) {
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+ /*
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+ * Spec says: bits [31:4] of the given address should point to
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+ * the 128-bit word containing the desired starting pixel,
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+ * and bits[3:0] should be between 0 and 11, indicating which
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+ * of the 12-pixels in that 128-bit word is the first pixel to be used
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+ */
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+ u32 aligned = vc4_state->src_x / 12;
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+ u32 last_bits = vc4_state->src_x % 12;
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+
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+ x_off = aligned * 16 + last_bits;
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hvs_format = HVS_PIXEL_FORMAT_YCBCR_10BIT;
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tiling = SCALER_CTL0_TILING_128B;
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- tile_w = 96;
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+ tile_w = 128;
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+ pix_per_tile = 96;
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} else {
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hvs_format = HVS_PIXEL_FORMAT_H264;
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@@ -842,17 +853,16 @@ static int vc4_plane_mode_set(struct drm
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default:
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break;
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}
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+ pix_per_tile = tile_w / fb->format->cpp[0];
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+ x_off = (vc4_state->src_x % pix_per_tile) /
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+ (i ? h_subsample : 1) * fb->format->cpp[i];
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}
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if (param > SCALER_TILE_HEIGHT_MASK) {
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DRM_DEBUG_KMS("SAND height too large (%d)\n",
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param);
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return -EINVAL;
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}
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-
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- pix_per_tile = tile_w / fb->format->cpp[0];
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tile = vc4_state->src_x / pix_per_tile;
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- x_off = vc4_state->src_x % pix_per_tile;
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-
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/* Adjust the base pointer to the first pixel to be scanned
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* out.
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*
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@@ -868,9 +878,7 @@ static int vc4_plane_mode_set(struct drm
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vc4_state->offsets[i] += src_y /
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(i ? v_subsample : 1) *
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tile_w;
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- vc4_state->offsets[i] += x_off /
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- (i ? h_subsample : 1) *
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- fb->format->cpp[i];
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+ vc4_state->offsets[i] += x_off & ~(i ? 1 : 0);
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}
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pitch0 = VC4_SET_FIELD(param, SCALER_TILE_HEIGHT);
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