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https://github.com/openwrt/openwrt.git
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b4c02c9998
Removed upstreamed patches:
generic/pending-5.4
445-mtd-spinand-gigadevice-Only-one-dummy-byte-in-QUA.patch
446-mtd-spinand-gigadevice-Add-QE-Bit.patch
pistachio/patches-5.4
150-pwm-img-Fix-null-pointer-access-in-probe.patch
Manually rebased:
layerscape/patches-5.4
801-audio-0011-Revert-ASoC-fsl_sai-add-of_match-data.patch
801-audio-0039-MLK-16224-6-ASoC-fsl_sai-fix-DSD-suspend-resume.patch
801-audio-0073-MLK-21957-3-ASoC-fsl_sai-add-bitcount-and-timestamp-.patch
820-usb-0009-usb-dwc3-Add-workaround-for-host-mode-VBUS-glitch-wh.patch
All modifications made by update_kernel.sh
Build system: x86_64
Build-tested: ipq806x/R7800, ath79/generic, bcm27xx/bcm2711,
mvebu (mamba, rango), x86_64, ramips/mt7621
Run-tested: ipq806x/R7800, mvebu (mamba, rango), x86_64, ramips (RT-AC57U)
No dmesg regressions, everything functional
Signed-off-by: John Audia <graysky@archlinux.us>
[alter 820-usb-0009-usb-dwc3-Add-workaround-for-host-mode-VBUS-glitch-wh]
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
62 lines
2.3 KiB
Diff
62 lines
2.3 KiB
Diff
From 86608c5578b7a276e0edcedc976c604e283fd177 Mon Sep 17 00:00:00 2001
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From: Marc Kleine-Budde <mkl@pengutronix.de>
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Date: Fri, 1 Mar 2019 11:12:13 +0100
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Subject: [PATCH] can: flexcan: rename macro FLEXCAN_IFLAG_MB() ->
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FLEXCAN_IFLAG2_MB()
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The macro FLEXCAN_IFLAG_MB() is always used for the iflag2 register, so
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rename it to FLEXCAN_IFLAG2_MB()
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Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
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---
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drivers/net/can/flexcan.c | 10 +++++-----
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1 file changed, 5 insertions(+), 5 deletions(-)
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--- a/drivers/net/can/flexcan.c
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+++ b/drivers/net/can/flexcan.c
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@@ -142,7 +142,7 @@
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#define FLEXCAN_TX_MB_RESERVED_OFF_FIFO 8
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#define FLEXCAN_TX_MB_RESERVED_OFF_TIMESTAMP 0
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#define FLEXCAN_RX_MB_OFF_TIMESTAMP_FIRST (FLEXCAN_TX_MB_RESERVED_OFF_TIMESTAMP + 1)
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-#define FLEXCAN_IFLAG_MB(x) BIT((x) & 0x1f)
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+#define FLEXCAN_IFLAG2_MB(x) BIT((x) & 0x1f)
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#define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW BIT(7)
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#define FLEXCAN_IFLAG_RX_FIFO_WARN BIT(6)
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#define FLEXCAN_IFLAG_RX_FIFO_AVAILABLE BIT(5)
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@@ -880,7 +880,7 @@ static inline u64 flexcan_read_reg_iflag
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u32 iflag1, iflag2;
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iflag2 = priv->read(®s->iflag2) & priv->reg_imask2_default &
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- ~FLEXCAN_IFLAG_MB(priv->tx_mb_idx);
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+ ~FLEXCAN_IFLAG2_MB(priv->tx_mb_idx);
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iflag1 = priv->read(®s->iflag1) & priv->reg_imask1_default;
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return (u64)iflag2 << 32 | iflag1;
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@@ -930,7 +930,7 @@ static irqreturn_t flexcan_irq(int irq,
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reg_iflag2 = priv->read(®s->iflag2);
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/* transmission complete interrupt */
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- if (reg_iflag2 & FLEXCAN_IFLAG_MB(priv->tx_mb_idx)) {
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+ if (reg_iflag2 & FLEXCAN_IFLAG2_MB(priv->tx_mb_idx)) {
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u32 reg_ctrl = priv->read(&priv->tx_mb->can_ctrl);
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handled = IRQ_HANDLED;
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@@ -942,7 +942,7 @@ static irqreturn_t flexcan_irq(int irq,
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/* after sending a RTR frame MB is in RX mode */
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priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
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&priv->tx_mb->can_ctrl);
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- priv->write(FLEXCAN_IFLAG_MB(priv->tx_mb_idx), ®s->iflag2);
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+ priv->write(FLEXCAN_IFLAG2_MB(priv->tx_mb_idx), ®s->iflag2);
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netif_wake_queue(dev);
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}
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@@ -1321,7 +1321,7 @@ static int flexcan_open(struct net_devic
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priv->tx_mb = flexcan_get_mb(priv, priv->tx_mb_idx);
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priv->reg_imask1_default = 0;
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- priv->reg_imask2_default = FLEXCAN_IFLAG_MB(priv->tx_mb_idx);
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+ priv->reg_imask2_default = FLEXCAN_IFLAG2_MB(priv->tx_mb_idx);
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priv->offload.mailbox_read = flexcan_mailbox_read;
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