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8b7abea2f6
This adds the necessary patches for 4.19 kernel. Upstreamed patches were dropped, backported upstreamed patches from 4.20. Drop Winbond ID patch since that NAND IC was upstreamed to use SPI-NAND framework and support for it was backported from 4.20. Rework ESSEDMA patches to compile under 4.19 due to timer changes, Clément Péron did the hard work and his changes were taken from the initial 4.19 PR. MR33 changes had to be manually refreshed to apply. Refresh other patches to apply. Signed-off-by: Robert Marko <robimarko@gmail.com> Remove
111 lines
2.6 KiB
Diff
111 lines
2.6 KiB
Diff
From bcb9ab4c2917e92114d2f4c2b1da97cdf15b471b Mon Sep 17 00:00:00 2001
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From: Matthew McClintock <mmcclint@codeaurora.org>
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Date: Wed, 25 Jul 2018 10:37:46 +0200
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Subject: [PATCH] ARM: dts: qcom: ipq4019: add cpu operating points for cpufreq
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support
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This adds some operating points for cpu frequeny scaling
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Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
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Signed-off-by: John Crispin <john@phrozen.org>
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Signed-off-by: Andy Gross <andy.gross@linaro.org>
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---
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arch/arm/boot/dts/qcom-ipq4019.dtsi | 54 ++++++++++++++---------------
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1 file changed, 26 insertions(+), 28 deletions(-)
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--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
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+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
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@@ -59,14 +59,8 @@
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reg = <0x0>;
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clocks = <&gcc GCC_APPS_CLK_SRC>;
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clock-frequency = <0>;
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- operating-points = <
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- /* kHz uV (fixed) */
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- 48000 1100000
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- 200000 1100000
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- 500000 1100000
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- 716000 1100000
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- >;
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clock-latency = <256000>;
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+ operating-points-v2 = <&cpu0_opp_table>;
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};
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cpu@1 {
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@@ -79,14 +73,8 @@
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reg = <0x1>;
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clocks = <&gcc GCC_APPS_CLK_SRC>;
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clock-frequency = <0>;
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- operating-points = <
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- /* kHz uV (fixed) */
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- 48000 1100000
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- 200000 1100000
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- 500000 1100000
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- 666000 1100000
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- >;
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clock-latency = <256000>;
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+ operating-points-v2 = <&cpu0_opp_table>;
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};
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cpu@2 {
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@@ -99,14 +87,8 @@
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reg = <0x2>;
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clocks = <&gcc GCC_APPS_CLK_SRC>;
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clock-frequency = <0>;
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- operating-points = <
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- /* kHz uV (fixed) */
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- 48000 1100000
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- 200000 1100000
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- 500000 1100000
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- 666000 1100000
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- >;
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clock-latency = <256000>;
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+ operating-points-v2 = <&cpu0_opp_table>;
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};
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cpu@3 {
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@@ -119,14 +101,8 @@
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reg = <0x3>;
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clocks = <&gcc GCC_APPS_CLK_SRC>;
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clock-frequency = <0>;
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- operating-points = <
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- /* kHz uV (fixed) */
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- 48000 1100000
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- 200000 1100000
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- 500000 1100000
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- 666000 1100000
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- >;
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clock-latency = <256000>;
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+ operating-points-v2 = <&cpu0_opp_table>;
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};
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L2: l2-cache {
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@@ -136,6 +112,28 @@
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};
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};
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+ cpu0_opp_table: opp_table0 {
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+ compatible = "operating-points-v2";
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+ opp-shared;
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+
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+ opp-48000000 {
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+ opp-hz = /bits/ 64 <48000000>;
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+ clock-latency-ns = <256000>;
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+ };
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+ opp-200000000 {
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+ opp-hz = /bits/ 64 <200000000>;
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+ clock-latency-ns = <256000>;
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+ };
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+ opp-500000000 {
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+ opp-hz = /bits/ 64 <500000000>;
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+ clock-latency-ns = <256000>;
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+ };
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+ opp-716000000 {
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+ opp-hz = /bits/ 64 <716000000>;
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+ clock-latency-ns = <256000>;
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+ };
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+ };
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+
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pmu {
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compatible = "arm,cortex-a7-pmu";
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interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) |
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