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73eeac49be
In the past few years, we have received several reports about SPI Flash not working properly. This is caused by excessively fast clock frequency. It's really annoying to fix them one by one. Let's reduce these aggressive frequencies to 50 MHz. This is a safe and suggested value in the vendor SDK. Signed-off-by: Shiji Yang <yangshiji66@qq.com>
221 lines
3.8 KiB
Plaintext
221 lines
3.8 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later
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#include "mt7621.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/leds/common.h>
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/ {
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compatible = "tplink,mr600-v2-eu", "mediatek,mt7621-soc";
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model = "TP-Link MR600 v2 (EU)";
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aliases {
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led-boot = &led_power;
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led-failsafe = &led_power;
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led-running = &led_power;
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led-upgrade = &led_power;
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label-mac-device = &gmac0;
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};
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chosen {
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bootargs = "console=ttyS0,115200";
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};
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keys {
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compatible = "gpio-keys";
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wlan {
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label = "wlan";
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gpios = <&gpio 3 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_WLAN>;
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};
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reset {
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label = "reset";
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gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_RESTART>;
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};
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};
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leds {
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compatible = "gpio-leds";
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led_power: power {
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function = LED_FUNCTION_POWER;
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color = <LED_COLOR_ID_WHITE>;
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gpios = <&gpio 6 GPIO_ACTIVE_LOW>;
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};
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wlan {
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function = LED_FUNCTION_WLAN;
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color = <LED_COLOR_ID_WHITE>;
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gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
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linux,default-trigger = "phy1tpt";
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};
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wan {
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function = LED_FUNCTION_WAN;
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color = <LED_COLOR_ID_WHITE>;
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gpios = <&gpio 8 GPIO_ACTIVE_LOW>;
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};
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signal1 {
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label = "white:signal1";
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gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
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};
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signal2 {
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label = "white:signal2";
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gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
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};
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signal3 {
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label = "white:signal3";
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gpios = <&gpio 10 GPIO_ACTIVE_LOW>;
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};
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4g {
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label = "white:4g";
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gpios = <&gpio 18 GPIO_ACTIVE_LOW>;
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};
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lan {
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function = LED_FUNCTION_LAN;
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color = <LED_COLOR_ID_WHITE>;
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gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
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};
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};
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};
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&spi0 {
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status = "okay";
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flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <50000000>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "uboot";
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reg = <0x00000 0x20000>;
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read-only;
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};
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partition@20000 {
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compatible = "openwrt,uimage";
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openwrt,offset = <512>; /* account for the 512-byte long header */
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label = "firmware";
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reg = <0x20000 0xfa0000>;
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};
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partition@fc0000 {
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label = "romfile";
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reg = <0xfc0000 0x10000>;
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read-only;
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nvmem-layout {
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compatible = "fixed-layout";
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#address-cells = <1>;
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#size-cells = <1>;
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macaddr_romfile_f100: romfile@f100 {
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compatible = "mac-base";
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reg = <0xf100 0x6>;
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#nvmem-cell-cells = <1>;
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};
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};
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};
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partition@fd0000 {
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label = "config";
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reg = <0xfd0000 0x10000>;
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read-only;
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};
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partition@fe0000 {
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label = "radio";
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reg = <0xfe0000 0x10000>;
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read-only;
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nvmem-layout {
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compatible = "fixed-layout";
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#address-cells = <1>;
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#size-cells = <1>;
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eeprom_radio_0: eeprom@0 {
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reg = <0x0 0x400>;
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};
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eeprom_radio_8000: eeprom@8000 {
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reg = <0x8000 0x4da8>;
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};
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};
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};
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};
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};
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};
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&pcie {
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status = "okay";
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};
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&pcie0 {
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mt76@0,0 {
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compatible = "mediatek,mt76";
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reg = <0x0000 0 0 0 0>;
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nvmem-cells = <&eeprom_radio_0>, <&macaddr_romfile_f100 0>;
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nvmem-cell-names = "eeprom", "mac-address";
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ieee80211-freq-limit = <2400000 2500000>;
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};
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};
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&pcie1 {
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mt76@0,0 {
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compatible = "mediatek,mt76";
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reg = <0x0000 0 0 0 0>;
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ieee80211-freq-limit = <5000000 6000000>;
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nvmem-cells = <&eeprom_radio_8000>, <&macaddr_romfile_f100 (-1)>;
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nvmem-cell-names = "eeprom", "mac-address";
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};
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};
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&gmac0 {
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nvmem-cells = <&macaddr_romfile_f100 0>;
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nvmem-cell-names = "mac-address";
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};
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&gmac1 {
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status = "okay";
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label = "wan";
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phy-handle = <ðphy4>;
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nvmem-cells = <&macaddr_romfile_f100 0>;
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nvmem-cell-names = "mac-address";
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};
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ðphy4 {
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/delete-property/ interrupts;
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};
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&switch0 {
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ports {
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port@1 {
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status = "okay";
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label = "lan1";
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};
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port@2 {
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status = "okay";
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label = "lan2";
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};
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port@3 {
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status = "okay";
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label = "lan3";
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};
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};
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};
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