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169 lines
4.2 KiB
C
169 lines
4.2 KiB
C
#ifndef __IDT_DMA_H__
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#define __IDT_DMA_H__
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/*******************************************************************************
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*
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* Copyright 2002 Integrated Device Technology, Inc.
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* All rights reserved.
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*
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* DMA register definition.
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*
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* File : $Id: dma.h,v 1.3 2002/06/06 18:34:03 astichte Exp $
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*
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* Author : ryan.holmQVist@idt.com
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* Date : 20011005
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* Update :
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* $Log: dma.h,v $
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* Revision 1.3 2002/06/06 18:34:03 astichte
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* Added XXX_PhysicalAddress and XXX_VirtualAddress
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*
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* Revision 1.2 2002/06/05 18:30:46 astichte
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* Removed IDTField
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*
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* Revision 1.1 2002/05/29 17:33:21 sysarch
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* jba File moved from vcode/include/idt/acacia
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*
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*
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******************************************************************************/
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enum
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{
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DMA0_PhysicalAddress = 0x18040000,
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DMA_PhysicalAddress = DMA0_PhysicalAddress, // Default
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DMA0_VirtualAddress = 0xb8040000,
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DMA_VirtualAddress = DMA0_VirtualAddress, // Default
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} ;
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/*
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* DMA descriptor (in physical memory).
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*/
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typedef struct DMAD_s
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{
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u32 control ; // Control. use DMAD_*
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u32 ca ; // Current Address.
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u32 devcs ; // Device control and status.
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u32 link ; // Next descriptor in chain.
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} volatile *DMAD_t ;
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enum
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{
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DMAD_size = sizeof (struct DMAD_s),
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DMAD_count_b = 0, // in DMAD_t -> control
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DMAD_count_m = 0x0003ffff, // in DMAD_t -> control
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DMAD_ds_b = 20, // in DMAD_t -> control
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DMAD_ds_m = 0x00300000, // in DMAD_t -> control
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DMAD_ds_ethRcv_v = 0,
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DMAD_ds_ethXmt_v = 0,
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DMAD_ds_memToFifo_v = 0,
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DMAD_ds_fifoToMem_v = 0,
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DMAD_ds_pciToMem_v = 0,
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DMAD_ds_memToPci_v = 0,
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DMAD_devcmd_b = 22, // in DMAD_t -> control
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DMAD_devcmd_m = 0x01c00000, // in DMAD_t -> control
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DMAD_devcmd_byte_v = 0, //memory-to-memory
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DMAD_devcmd_halfword_v = 1, //memory-to-memory
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DMAD_devcmd_word_v = 2, //memory-to-memory
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DMAD_devcmd_2words_v = 3, //memory-to-memory
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DMAD_devcmd_4words_v = 4, //memory-to-memory
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DMAD_devcmd_6words_v = 5, //memory-to-memory
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DMAD_devcmd_8words_v = 6, //memory-to-memory
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DMAD_devcmd_16words_v = 7, //memory-to-memory
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DMAD_cof_b = 25, // chain on finished
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DMAD_cof_m = 0x02000000, //
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DMAD_cod_b = 26, // chain on done
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DMAD_cod_m = 0x04000000, //
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DMAD_iof_b = 27, // interrupt on finished
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DMAD_iof_m = 0x08000000, //
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DMAD_iod_b = 28, // interrupt on done
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DMAD_iod_m = 0x10000000, //
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DMAD_t_b = 29, // terminated
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DMAD_t_m = 0x20000000, //
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DMAD_d_b = 30, // done
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DMAD_d_m = 0x40000000, //
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DMAD_f_b = 31, // finished
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DMAD_f_m = 0x80000000, //
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} ;
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/*
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* DMA register (within Internal Register Map).
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*/
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struct DMA_Chan_s
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{
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u32 dmac ; // Control.
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u32 dmas ; // Status.
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u32 dmasm ; // Mask.
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u32 dmadptr ; // Descriptor pointer.
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u32 dmandptr ; // Next descriptor pointer.
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};
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typedef struct DMA_Chan_s volatile *DMA_Chan_t ;
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//DMA_Channels use DMACH_count instead
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enum
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{
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DMAC_run_b = 0, //
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DMAC_run_m = 0x00000001, //
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DMAC_dm_b = 1, // done mask
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DMAC_dm_m = 0x00000002, //
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DMAC_mode_b = 2, //
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DMAC_mode_m = 0x0000000c, //
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DMAC_mode_auto_v = 0,
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DMAC_mode_burst_v = 1,
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DMAC_mode_transfer_v = 2, //usually used
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DMAC_mode_reserved_v = 3,
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DMAC_a_b = 4, //
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DMAC_a_m = 0x00000010, //
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DMAS_f_b = 0, // finished (sticky)
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DMAS_f_m = 0x00000001, //
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DMAS_d_b = 1, // done (sticky)
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DMAS_d_m = 0x00000002, //
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DMAS_c_b = 2, // chain (sticky)
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DMAS_c_m = 0x00000004, //
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DMAS_e_b = 3, // error (sticky)
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DMAS_e_m = 0x00000008, //
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DMAS_h_b = 4, // halt (sticky)
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DMAS_h_m = 0x00000010, //
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DMASM_f_b = 0, // finished (1=mask)
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DMASM_f_m = 0x00000001, //
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DMASM_d_b = 1, // done (1=mask)
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DMASM_d_m = 0x00000002, //
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DMASM_c_b = 2, // chain (1=mask)
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DMASM_c_m = 0x00000004, //
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DMASM_e_b = 3, // error (1=mask)
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DMASM_e_m = 0x00000008, //
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DMASM_h_b = 4, // halt (1=mask)
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DMASM_h_m = 0x00000010, //
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} ;
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/*
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* DMA channel definitions
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*/
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enum
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{
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DMACH_ethRcv = 0,
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DMACH_ethXmt = 1,
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DMACH_memToFifo = 2,
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DMACH_fifoToMem = 3,
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DMACH_pciToMem = 4,
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DMACH_memToPci = 5,
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DMACH_count //must be last
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};
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typedef struct DMAC_s
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{
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struct DMA_Chan_s ch [DMACH_count] ; //use ch[DMACH_]
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} volatile *DMA_t ;
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#endif // __IDT_DMA_H__
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