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Removed because they are upstream: generic/pending-5.15/110-v6.3-0001-spidev-Add-Silicon-Labs-EM3581-device-compatible.patch https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=linux-5.15.y&id=bff165a3993683daddf3f00563960e7675966f91 ipq807x/patches-5.15/0004-v5.16-arm64-dts-qcom-msm8996-Move-clock-cells-to-QMP-PHY-c.patch https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=linux-5.15.y&id=32f0e52f16d45d743b473659329f93d4a27c68bf Manually adapted: bcm27xx/patches-5.15/950-0040-spi-spidev-Completely-disable-the-spidev-warning.patch bcm27xx/patches-5.15/950-0578-spi-spidev-Restore-loading-from-Device-Tree.patch generic/pending-5.15/110-v6.3-0002-spidev-Add-Silicon-Labs-SI3210-device-compatible.patch Adapt kernel configuration for newly added option CONFIG_ARM64_ERRATUM_3194386. The leddev_list_lock attribute changed from rwlock_t to spinlock_t in: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=linux-5.15.y&id=590304b798a3b89e716b6b564f8ad14bc9373d93 Link: https://github.com/openwrt/openwrt/pull/16366 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
28 lines
1.1 KiB
Diff
28 lines
1.1 KiB
Diff
From: Tobias Waldekranz <tobias@waldekranz.com>
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Subject: [RFC net-next 7/7] net: dsa: mv88e6xxx: Request assisted learning on CPU port
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Date: Sat, 16 Jan 2021 02:25:15 +0100
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Archived-At: <https://lore.kernel.org/netdev/20210116012515.3152-8-tobias@waldekranz.com/>
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While the hardware is capable of performing learning on the CPU port,
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it requires alot of additions to the bridge's forwarding path in order
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to handle multi-destination traffic correctly.
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Until that is in place, opt for the next best thing and let DSA sync
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the relevant addresses down to the hardware FDB.
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Signed-off-by: Tobias Waldekranz <tobias@waldekranz.com>
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---
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drivers/net/dsa/mv88e6xxx/chip.c | 1 +
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1 file changed, 1 insertion(+)
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--- a/drivers/net/dsa/mv88e6xxx/chip.c
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+++ b/drivers/net/dsa/mv88e6xxx/chip.c
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@@ -6386,6 +6386,7 @@ static int mv88e6xxx_register_switch(str
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ds->ops = &mv88e6xxx_switch_ops;
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ds->ageing_time_min = chip->info->age_time_coeff;
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ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX;
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+ ds->assisted_learning_on_cpu_port = true;
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/* Some chips support up to 32, but that requires enabling the
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* 5-bit port mode, which we do not support. 640k^W16 ought to
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