John Crispin 4d6c4994fc ar71xx: Use PHY fixups for Open Mesh MR1750
The delays of PHY/MAC on the MR1750 are done by u-boot and OpenWrt in
different ways. u-boot only modifies the ETH_CFG of the QCA955x based on
the link speed. But OpenWrt can only modify the PHY delays based on the
link speed.

This can lead to communication problems when u-boot initializes the ETH_CFG
for a specific link speed (e.g. 10BASE-T) but then OpenWrt the sets the PHY
delays to an incompatible value.

Instead reset the ETH_CFG delay bits of the QCA955x to a specific value and
only rely on the AT803x PHY settings.

Signed-off-by: Sven Eckelmann <sven.eckelmann@open-mesh.com>

SVN-Revision: 49031
2016-03-16 09:27:14 +00:00
2016-02-07 13:29:16 +00:00
2015-07-14 09:57:45 +00:00
2016-03-08 18:11:37 +00:00
2016-03-10 19:11:41 +00:00
2007-02-26 01:05:09 +00:00
2016-03-20 17:29:15 +01:00
2016-01-28 22:42:18 +00:00

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