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86 lines
2.6 KiB
Diff
86 lines
2.6 KiB
Diff
From 98d2c4ca97dde30616fa78ad5677825b1966cec6 Mon Sep 17 00:00:00 2001
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From: Claudiu Beznea <claudiu.beznea@microchip.com>
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Date: Wed, 15 Sep 2021 10:48:35 +0300
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Subject: [PATCH 232/247] ARM: dts: at91: sama7g5ek: use proper slew-rate
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settings for GMACs
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Datasheet chapter "EMAC Timings" specifies that while in 3.3V domain
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GMAC's MDIO pins should be configured with slew-rate enabled, while the
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data + signaling pins should be configured with slew-rate disabled when
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GMAC works in RGMII or RMII modes. The pin controller for SAMA7G5 sets
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the slew-rate as enabled for all pins. Adapt the device tree to comply
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with these.
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Fixes: 7540629e2fc7 ("ARM: dts: at91: add sama7g5 SoC DT and sama7g5-ek")
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Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
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Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
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Link: https://lore.kernel.org/r/20210915074836.6574-2-claudiu.beznea@microchip.com
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---
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arch/arm/boot/dts/at91-sama7g5ek.dts | 28 ++++++++++++++++++++++------
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1 file changed, 22 insertions(+), 6 deletions(-)
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--- a/arch/arm/boot/dts/at91-sama7g5ek.dts
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+++ b/arch/arm/boot/dts/at91-sama7g5ek.dts
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@@ -355,7 +355,10 @@
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-names = "default";
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- pinctrl-0 = <&pinctrl_gmac0_default &pinctrl_gmac0_txck_default &pinctrl_gmac0_phy_irq>;
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+ pinctrl-0 = <&pinctrl_gmac0_default
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+ &pinctrl_gmac0_mdio_default
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+ &pinctrl_gmac0_txck_default
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+ &pinctrl_gmac0_phy_irq>;
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phy-mode = "rgmii-id";
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status = "okay";
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@@ -370,7 +373,9 @@
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-names = "default";
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- pinctrl-0 = <&pinctrl_gmac1_default &pinctrl_gmac1_phy_irq>;
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+ pinctrl-0 = <&pinctrl_gmac1_default
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+ &pinctrl_gmac1_mdio_default
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+ &pinctrl_gmac1_phy_irq>;
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phy-mode = "rmii";
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status = "okay";
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@@ -425,14 +430,20 @@
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<PIN_PA15__G0_TXEN>,
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<PIN_PA30__G0_RXCK>,
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<PIN_PA18__G0_RXDV>,
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- <PIN_PA22__G0_MDC>,
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- <PIN_PA23__G0_MDIO>,
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<PIN_PA25__G0_125CK>;
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+ slew-rate = <0>;
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+ bias-disable;
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+ };
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+
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+ pinctrl_gmac0_mdio_default: gmac0_mdio_default {
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+ pinmux = <PIN_PA22__G0_MDC>,
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+ <PIN_PA23__G0_MDIO>;
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bias-disable;
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};
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pinctrl_gmac0_txck_default: gmac0_txck_default {
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pinmux = <PIN_PA24__G0_TXCK>;
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+ slew-rate = <0>;
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bias-pull-up;
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};
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@@ -449,8 +460,13 @@
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<PIN_PD25__G1_RX0>,
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<PIN_PD26__G1_RX1>,
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<PIN_PD27__G1_RXER>,
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- <PIN_PD24__G1_RXDV>,
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- <PIN_PD28__G1_MDC>,
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+ <PIN_PD24__G1_RXDV>;
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+ slew-rate = <0>;
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+ bias-disable;
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+ };
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+
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+ pinctrl_gmac1_mdio_default: gmac1_mdio_default {
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+ pinmux = <PIN_PD28__G1_MDC>,
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<PIN_PD29__G1_MDIO>;
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bias-disable;
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};
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