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118 lines
3.6 KiB
Diff
118 lines
3.6 KiB
Diff
From 2cd84ddf0e9623c6bc723b1df368cd8b16a3a8e2 Mon Sep 17 00:00:00 2001
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From: Claudiu Beznea <claudiu.beznea@microchip.com>
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Date: Mon, 30 Aug 2021 13:09:27 +0300
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Subject: [PATCH 228/247] ARM: at91: pm: switch backup area to vbat in backup
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mode
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Backup area is now switched to VDDIN33 at boot (with the help of
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bootloader). When switching to backup mode we need to switch backup area
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to VBAT as all the other power sources are cut off. The resuming from
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backup mode is done with the help of bootloader, so there is no need to
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do something particular in Linux to restore backup area power source.
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Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
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Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
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Link: https://lore.kernel.org/r/20210830100927.22711-1-claudiu.beznea@microchip.com
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---
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arch/arm/mach-at91/pm.c | 52 +++++++++++++++++++++++++++++++++++++++++
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1 file changed, 52 insertions(+)
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--- a/arch/arm/mach-at91/pm.c
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+++ b/arch/arm/mach-at91/pm.c
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@@ -47,12 +47,26 @@ struct at91_pm_bu {
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unsigned long ddr_phy_calibration[BACKUP_DDR_PHY_CALIBRATION];
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};
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+/*
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+ * struct at91_pm_sfrbu_offsets: registers mapping for SFRBU
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+ * @pswbu: power switch BU control registers
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+ */
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+struct at91_pm_sfrbu_regs {
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+ struct {
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+ u32 key;
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+ u32 ctrl;
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+ u32 state;
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+ u32 softsw;
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+ } pswbu;
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+};
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+
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/**
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* struct at91_soc_pm - AT91 SoC power management data structure
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* @config_shdwc_ws: wakeup sources configuration function for SHDWC
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* @config_pmc_ws: wakeup srouces configuration function for PMC
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* @ws_ids: wakup sources of_device_id array
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* @data: PM data to be used on last phase of suspend
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+ * @sfrbu_regs: SFRBU registers mapping
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* @bu: backup unit mapped data (for backup mode)
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* @memcs: memory chip select
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*/
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@@ -62,6 +76,7 @@ struct at91_soc_pm {
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const struct of_device_id *ws_ids;
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struct at91_pm_bu *bu;
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struct at91_pm_data data;
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+ struct at91_pm_sfrbu_regs sfrbu_regs;
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void *memcs;
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};
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@@ -356,9 +371,36 @@ static int at91_suspend_finish(unsigned
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return 0;
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}
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+static void at91_pm_switch_ba_to_vbat(void)
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+{
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+ unsigned int offset = offsetof(struct at91_pm_sfrbu_regs, pswbu);
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+ unsigned int val;
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+
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+ /* Just for safety. */
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+ if (!soc_pm.data.sfrbu)
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+ return;
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+
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+ val = readl(soc_pm.data.sfrbu + offset);
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+
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+ /* Already on VBAT. */
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+ if (!(val & soc_pm.sfrbu_regs.pswbu.state))
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+ return;
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+
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+ val &= ~soc_pm.sfrbu_regs.pswbu.softsw;
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+ val |= soc_pm.sfrbu_regs.pswbu.key | soc_pm.sfrbu_regs.pswbu.ctrl;
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+ writel(val, soc_pm.data.sfrbu + offset);
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+
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+ /* Wait for update. */
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+ val = readl(soc_pm.data.sfrbu + offset);
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+ while (val & soc_pm.sfrbu_regs.pswbu.state)
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+ val = readl(soc_pm.data.sfrbu + offset);
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+}
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+
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static void at91_pm_suspend(suspend_state_t state)
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{
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if (soc_pm.data.mode == AT91_PM_BACKUP) {
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+ at91_pm_switch_ba_to_vbat();
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+
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cpu_suspend(0, at91_suspend_finish);
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/* The SRAM is lost between suspend cycles */
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@@ -1155,6 +1197,11 @@ void __init sama5d2_pm_init(void)
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soc_pm.ws_ids = sama5d2_ws_ids;
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soc_pm.config_shdwc_ws = at91_sama5d2_config_shdwc_ws;
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soc_pm.config_pmc_ws = at91_sama5d2_config_pmc_ws;
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+
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+ soc_pm.sfrbu_regs.pswbu.key = (0x4BD20C << 8);
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+ soc_pm.sfrbu_regs.pswbu.ctrl = BIT(0);
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+ soc_pm.sfrbu_regs.pswbu.softsw = BIT(1);
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+ soc_pm.sfrbu_regs.pswbu.state = BIT(3);
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}
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void __init sama7_pm_init(void)
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@@ -1185,6 +1232,11 @@ void __init sama7_pm_init(void)
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soc_pm.ws_ids = sama7g5_ws_ids;
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soc_pm.config_pmc_ws = at91_sam9x60_config_pmc_ws;
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+
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+ soc_pm.sfrbu_regs.pswbu.key = (0x4BD20C << 8);
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+ soc_pm.sfrbu_regs.pswbu.ctrl = BIT(0);
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+ soc_pm.sfrbu_regs.pswbu.softsw = BIT(1);
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+ soc_pm.sfrbu_regs.pswbu.state = BIT(2);
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}
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static int __init at91_pm_modes_select(char *str)
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