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0b2c1d8b9a
ath25 requires a 88E6060 driver to support boards such as Fonera 2.0g (FON2202). The swconfig based mvswitch driver has not yet been ported to the 5.10 kernel as the only user is the ath25 target while all other targets have been switched to the upstream DSA implementation. Switching ath25 to the DSA implementation is a complex task, since we need either per-board platform data or DTS support. ath25 lacks both of them and builds only a single generic image. So we need to keep the swconfig driver implementation to easly and quickly port ath25 to the 5.10 kernel. Since porting the mvswitch driver to 5.10 as a generic driver is not an option, and since the ath25 is its only user, make mvswitch a target specific driver to be able to port it to the 5.10 kernel as part of the kernel version update of the target. This will allow us quickly migrate to the next kernel version and not delay the next firmware release. Suggested-by: Felix Fietkau <nbd@nbd.name> Signed-off-by: Sergey Ryazanov <ryazanov.s.a@gmail.com>
146 lines
4.1 KiB
C
146 lines
4.1 KiB
C
/*
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* Marvell 88E6060 switch driver
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* Copyright (c) 2008 Felix Fietkau <nbd@nbd.name>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License v2 as published by the
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* Free Software Foundation
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*/
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#ifndef __MVSWITCH_H
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#define __MVSWITCH_H
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#define MV_HEADER_SIZE 2
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#define MV_HEADER_PORTS_M 0x001f
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#define MV_HEADER_PORTS_S 0
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#define MV_HEADER_VLAN_M 0xf000
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#define MV_HEADER_VLAN_S 12
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#define MV_TRAILER_SIZE 4
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#define MV_TRAILER_PORTS_M 0x1f
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#define MV_TRAILER_PORTS_S 16
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#define MV_TRAILER_FLAGS_S 24
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#define MV_TRAILER_OVERRIDE 0x80
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#define MV_PORTS 5
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#define MV_WANPORT 4
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#define MV_CPUPORT 5
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#define MV_BASE 0x10
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#define MV_PHYPORT_BASE (MV_BASE + 0x0)
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#define MV_PHYPORT(_n) (MV_PHYPORT_BASE + (_n))
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#define MV_SWITCHPORT_BASE (MV_BASE + 0x8)
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#define MV_SWITCHPORT(_n) (MV_SWITCHPORT_BASE + (_n))
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#define MV_SWITCHREGS (MV_BASE + 0xf)
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enum {
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MV_PHY_CONTROL = 0x00,
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MV_PHY_STATUS = 0x01,
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MV_PHY_IDENT0 = 0x02,
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MV_PHY_IDENT1 = 0x03,
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MV_PHY_ANEG = 0x04,
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MV_PHY_LINK_ABILITY = 0x05,
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MV_PHY_ANEG_EXPAND = 0x06,
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MV_PHY_XMIT_NEXTP = 0x07,
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MV_PHY_LINK_NEXTP = 0x08,
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MV_PHY_CONTROL1 = 0x10,
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MV_PHY_STATUS1 = 0x11,
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MV_PHY_INTR_EN = 0x12,
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MV_PHY_INTR_STATUS = 0x13,
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MV_PHY_INTR_PORT = 0x14,
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MV_PHY_RECV_COUNTER = 0x16,
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MV_PHY_LED_PARALLEL = 0x16,
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MV_PHY_LED_STREAM = 0x17,
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MV_PHY_LED_CTRL = 0x18,
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MV_PHY_LED_OVERRIDE = 0x19,
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MV_PHY_VCT_CTRL = 0x1a,
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MV_PHY_VCT_STATUS = 0x1b,
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MV_PHY_CONTROL2 = 0x1e
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};
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#define MV_PHYREG(_type, _port) MV_PHYPORT(_port), MV_PHY_##_type
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enum {
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MV_PORT_STATUS = 0x00,
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MV_PORT_IDENT = 0x03,
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MV_PORT_CONTROL = 0x04,
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MV_PORT_VLANMAP = 0x06,
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MV_PORT_ASSOC = 0x0b,
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MV_PORT_RXCOUNT = 0x10,
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MV_PORT_TXCOUNT = 0x11,
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};
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#define MV_PORTREG(_type, _port) MV_SWITCHPORT(_port), MV_PORT_##_type
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enum {
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MV_PORTCTRL_BLOCK = (1 << 0),
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MV_PORTCTRL_LEARN = (2 << 0),
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MV_PORTCTRL_ENABLED = (3 << 0),
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MV_PORTCTRL_VLANTUN = (1 << 7), /* Enforce VLANs on packets */
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MV_PORTCTRL_RXTR = (1 << 8), /* Enable Marvell packet trailer for ingress */
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MV_PORTCTRL_HEADER = (1 << 11), /* Enable Marvell packet header mode for port */
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MV_PORTCTRL_TXTR = (1 << 14), /* Enable Marvell packet trailer for egress */
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MV_PORTCTRL_FORCEFL = (1 << 15), /* force flow control */
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};
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#define MV_PORTVLAN_ID(_n) (((_n) & 0xf) << 12)
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#define MV_PORTVLAN_PORTS(_n) ((_n) & 0x3f)
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#define MV_PORTASSOC_PORTS(_n) ((_n) & 0x1f)
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#define MV_PORTASSOC_MONITOR (1 << 15)
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enum {
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MV_SWITCH_MAC0 = 0x01,
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MV_SWITCH_MAC1 = 0x02,
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MV_SWITCH_MAC2 = 0x03,
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MV_SWITCH_CTRL = 0x04,
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MV_SWITCH_ATU_CTRL = 0x0a,
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MV_SWITCH_ATU_OP = 0x0b,
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MV_SWITCH_ATU_DATA = 0x0c,
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MV_SWITCH_ATU_MAC0 = 0x0d,
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MV_SWITCH_ATU_MAC1 = 0x0e,
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MV_SWITCH_ATU_MAC2 = 0x0f,
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};
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#define MV_SWITCHREG(_type) MV_SWITCHREGS, MV_SWITCH_##_type
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enum {
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MV_SWITCHCTL_EEIE = (1 << 0), /* EEPROM interrupt enable */
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MV_SWITCHCTL_PHYIE = (1 << 1), /* PHY interrupt enable */
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MV_SWITCHCTL_ATUDONE= (1 << 2), /* ATU done interrupt enable */
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MV_SWITCHCTL_ATUIE = (1 << 3), /* ATU interrupt enable */
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MV_SWITCHCTL_CTRMODE= (1 << 8), /* statistics for rx and tx errors */
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MV_SWITCHCTL_RELOAD = (1 << 9), /* reload registers from eeprom */
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MV_SWITCHCTL_MSIZE = (1 << 10), /* increase maximum frame size */
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MV_SWITCHCTL_DROP = (1 << 13), /* discard frames with excessive collisions */
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};
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enum {
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#define MV_ATUCTL_AGETIME_MIN 16
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#define MV_ATUCTL_AGETIME_MAX 4080
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#define MV_ATUCTL_AGETIME(_n) ((((_n) / 16) & 0xff) << 4)
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MV_ATUCTL_ATU_256 = (0 << 12),
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MV_ATUCTL_ATU_512 = (1 << 12),
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MV_ATUCTL_ATU_1K = (2 << 12),
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MV_ATUCTL_ATUMASK = (3 << 12),
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MV_ATUCTL_NO_LEARN = (1 << 14),
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MV_ATUCTL_RESET = (1 << 15),
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};
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enum {
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#define MV_ATUOP_DBNUM(_n) ((_n) & 0x0f)
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MV_ATUOP_NOOP = (0 << 12),
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MV_ATUOP_FLUSH_ALL = (1 << 12),
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MV_ATUOP_FLUSH_U = (2 << 12),
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MV_ATUOP_LOAD_DB = (3 << 12),
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MV_ATUOP_GET_NEXT = (4 << 12),
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MV_ATUOP_FLUSH_DB = (5 << 12),
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MV_ATUOP_FLUSH_DB_UU= (6 << 12),
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MV_ATUOP_INPROGRESS = (1 << 15),
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};
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#define MV_IDENT_MASK 0xfff0
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#define MV_IDENT_VALUE 0x0600
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#endif
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