openwrt/target/linux/ath79/dts/ar7161_dlink_dir-825-b1.dts
Adrian Schmutzler 7054721cf9 ath79: enable UART in SoC DTSI files
The uart node is enabled on all devices except one (GL-USB150 *).
Thus, let's not have a few hundred nodes to enable it, but do not
disable it in the first place.

Where the majority of devices is using it, also move the serial0
alias to the DTSI.

*) Since GL-USB150 even defines serial0 alias, the missing uart
   is probably just a mistake. Anyway, disable it for now so this
   patch stays cosmetic.

Apply this to 21.02 as well to remove an unnecessary backporting
pitfall.

Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
(cherry picked from commit 3a4b751110)
2021-02-25 14:42:11 +01:00

230 lines
3.6 KiB
Plaintext

// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "ar7100.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
compatible = "dlink,dir-825-b1", "qca,ar7161";
model = "D-Link DIR825B1";
aliases {
led-boot = &led_power_orange;
led-failsafe = &led_power_orange;
led-running = &led_power_blue;
led-upgrade = &led_power_orange;
};
extosc: ref {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-output-names = "ref";
clock-frequency = <40000000>;
};
leds {
compatible = "gpio-leds";
usb {
label = "blue:usb";
gpios = <&gpio 0 GPIO_ACTIVE_LOW>;
trigger-sources = <&usb_ohci_port>, <&usb_ehci_port>;
linux,default-trigger = "usbport";
};
led_power_orange: power_orange {
label = "orange:power";
gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
default-state = "on";
};
led_power_blue: power_blue {
label = "blue:power";
gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
};
wps {
label = "blue:wps";
gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
};
planet_orange {
label = "orange:planet";
gpios = <&gpio 6 GPIO_ACTIVE_LOW>;
};
planet_blue {
label = "blue:planet";
gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
};
};
ath9k-leds {
compatible = "gpio-leds";
wlan2g {
label = "blue:wlan2g";
gpios = <&ath9k0 5 GPIO_ACTIVE_LOW>;
linux,default-trigger = "phy0tpt";
};
wlan5g {
label = "blue:wlan5g";
gpios = <&ath9k1 5 GPIO_ACTIVE_LOW>;
linux,default-trigger = "phy1tpt";
};
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
linux,code = <KEY_RESTART>;
gpios = <&gpio 3 GPIO_ACTIVE_LOW>;
};
wps {
label = "wps";
linux,code = <KEY_WPS_BUTTON>;
gpios = <&gpio 8 GPIO_ACTIVE_LOW>;
};
};
rtl8366s {
compatible = "realtek,rtl8366s";
gpio-sda = <&gpio 5 GPIO_ACTIVE_HIGH>;
gpio-sck = <&gpio 7 GPIO_ACTIVE_HIGH>;
realtek,initvals = <0x06 0x0108>;
mdio-bus {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
phy-mask = <0x10>;
phy4: ethernet-phy@4 {
reg = <4>;
phy-mode = "rgmii";
};
};
};
};
&usb1 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
usb_ohci_port: port@1 {
reg = <1>;
#trigger-source-cells = <0>;
};
};
&usb2 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
usb_ehci_port: port@1 {
reg = <1>;
#trigger-source-cells = <0>;
};
};
&usb_phy {
status = "okay";
};
&pcie0 {
status = "okay";
ath9k0: wifi@0,11 {
compatible = "pci168c,0029";
reg = <0x8800 0 0 0 0>;
qca,no-eeprom;
#gpio-cells = <2>;
gpio-controller;
};
ath9k1: wifi@0,12 {
compatible = "pci168c,0029";
reg = <0x9000 0 0 0 0>;
qca,no-eeprom;
#gpio-cells = <2>;
gpio-controller;
};
};
&pll {
clocks = <&extosc>;
};
&spi {
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <25000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "u-boot";
reg = <0x000000 0x040000>;
read-only;
};
partition@40000 {
label = "config";
reg = <0x040000 0x010000>;
read-only;
};
partition@50000 {
compatible = "denx,uimage";
label = "firmware";
reg = <0x050000 0x610000>;
};
partition@660000 {
label = "caldata";
reg = <0x660000 0x010000>;
read-only;
};
partition@670000 {
label = "unknown";
reg = <0x670000 0x190000>;
read-only;
};
};
};
};
&eth0 {
status = "okay";
pll-data = <0x11110000 0x00001099 0x00991099>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
&eth1 {
status = "okay";
pll-data = <0x11110000 0x00001099 0x00991099>;
phy-handle = <&phy4>;
};