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94 lines
3.3 KiB
Diff
94 lines
3.3 KiB
Diff
From 6075bbc75e55258a762d618cd459dbe0dd38aff9 Mon Sep 17 00:00:00 2001
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From: Claudiu Beznea <claudiu.beznea@microchip.com>
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Date: Thu, 30 Sep 2021 18:42:19 +0300
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Subject: [PATCH 231/247] ARM: at91: pm: preload base address of controllers in
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tlb
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In suspend/resume procedure for AT91 architecture different controllers
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(PMC, SHDWC, RAM, RAM PHY, SFRBU) are accessed to do the proper settings
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for power saving. Commit f0bbf17958e8 ("ARM: at91: pm: add self-refresh
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support for sama7g5") introduced the access to RAMC PHY controller for
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SAMA7G5. The access to this controller is done after RAMC ports are
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closed, thus any TLB walk necessary for RAMC PHY virtual address will
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fail. In the development branch this was not encountered. However, on
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current kernel the issue is reproducible.
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To solve the issue the previous mechanism of pre-loading the TLB with
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the RAMC PHY virtual address has been used. However, only the addition
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of this new pre-load breaks the functionality for ARMv5 based
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devices (SAM9X60). This behavior has been encountered previously
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while debugging this code and using the same mechanism for pre-loading
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address for different controllers (e.g. pin controller, the assumption
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being that other requested translations are replaced from TLB).
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To solve this new issue the TLB flush + the extension of pre-loading
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the rest of controllers to TLB (e.g. PMC, RAMC) has been added. The
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rest of the controllers should have been pre-loaded previously, anyway.
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Fixes: f0bbf17958e8 ("ARM: at91: pm: add self-refresh support for sama7g5")
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Depends-on: e42cbbe5c9a2 ("ARM: at91: pm: group constants and addresses loading")
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Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
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Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
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Link: https://lore.kernel.org/r/20210930154219.2214051-4-claudiu.beznea@microchip.com
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---
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arch/arm/mach-at91/pm_suspend.S | 25 ++++++++++++++++++++++++-
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1 file changed, 24 insertions(+), 1 deletion(-)
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--- a/arch/arm/mach-at91/pm_suspend.S
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+++ b/arch/arm/mach-at91/pm_suspend.S
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@@ -1014,6 +1014,10 @@ ENTRY(at91_pm_suspend_in_sram)
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mov tmp1, #0
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mcr p15, 0, tmp1, c7, c10, 4
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+ /* Flush tlb. */
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+ mov r4, #0
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+ mcr p15, 0, r4, c8, c7, 0
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+
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ldr tmp1, [r0, #PM_DATA_PMC_MCKR_OFFSET]
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str tmp1, .mckr_offset
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ldr tmp1, [r0, #PM_DATA_PMC_VERSION]
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@@ -1023,23 +1027,42 @@ ENTRY(at91_pm_suspend_in_sram)
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ldr tmp1, [r0, #PM_DATA_MODE]
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str tmp1, .pm_mode
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+ /*
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+ * ldrne below are here to preload their address in the TLB as access
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+ * to RAM may be limited while in self-refresh.
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+ */
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ldr tmp1, [r0, #PM_DATA_PMC]
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str tmp1, .pmc_base
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+ cmp tmp1, #0
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+ ldrne tmp2, [tmp1, #0]
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+
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ldr tmp1, [r0, #PM_DATA_RAMC0]
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str tmp1, .sramc_base
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+ cmp tmp1, #0
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+ ldrne tmp2, [tmp1, #0]
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+
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ldr tmp1, [r0, #PM_DATA_RAMC1]
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str tmp1, .sramc1_base
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+ cmp tmp1, #0
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+ ldrne tmp2, [tmp1, #0]
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+
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+#ifndef CONFIG_SOC_SAM_V4_V5
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+ /* ldrne below are here to preload their address in the TLB */
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ldr tmp1, [r0, #PM_DATA_RAMC_PHY]
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str tmp1, .sramc_phy_base
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- /* Both ldrne below are here to preload their address in the TLB */
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+ cmp tmp1, #0
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+ ldrne tmp2, [tmp1, #0]
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+
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ldr tmp1, [r0, #PM_DATA_SHDWC]
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str tmp1, .shdwc
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cmp tmp1, #0
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ldrne tmp2, [tmp1, #0]
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+
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ldr tmp1, [r0, #PM_DATA_SFRBU]
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str tmp1, .sfrbu
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cmp tmp1, #0
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ldrne tmp2, [tmp1, #0x10]
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+#endif
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/* Active the self-refresh mode */
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at91_sramc_self_refresh_ena
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