openwrt/target/linux/ipq807x/patches-5.15/0077-v6.0-PCI-qcom-Add-IPQ60xx-support.patch
John Audia 228e0e1039 kernel: bump 5.15 to 5.15.111
Removed upstreamed:
	01. backport-5.15/424-v6.4-0001-mtd-core-provide-unique-name-for-nvmem-device-take-t.patch
	02. backport-5.15/424-v6.4-0002-mtd-core-fix-nvmem-error-reporting.patch
	03. generic-backport/424-v6.4-0003-mtd-core-fix-error-path-for-nvmem-provider.patch
	04. generic-backport/828-v6.4-0001-of-Fix-modalias-string-generation.patch
	05. bcm4908/patches-5.15/031-v5.17-0002-arm64-dts-broadcom-bcm4908-add-DT-for-Netgear-RAXE50.patch
	06. bcm4908/patches-5.15/033-v6.0-0001-arm64-dts-Add-DTS-files-for-bcmbca-SoC-BCM63158.patchgit
	07. bcm4908/patches-5.15/033-v6.0-0002-arm64-dts-Add-DTS-files-for-bcmbca-SoC-BCM4912.patchgita
	08. bcm4908/patches-5.15/033-v6.0-0010-arm64-dts-Add-base-DTS-file-for-bcmbca-device-Asus-G.patchgit
	09. bcm4908/patches-5.15/034-v6.1-0005-arm64-dts-Move-BCM4908-dts-to-bcmbca-folder.patch
	10. bcm4908/patches-5.15/036-v6.4-0002-arm64-dts-broadcom-bcmbca-bcm4908-fix-NAND-interrupt.patch
	11. bcm4908/patches-5.15/036-v6.4-0004-arm64-dts-broadcom-bcmbca-bcm4908-fix-procmon-nodena.patch
	12. ipq806x/patches-5.15/104-v6.0-06-ARM-dts-qcom-ipq8064-reduce-pci-IO-size-to-64K.patch

Manually rebased:
	bcm27xx/patches-5.15/950-0078-BCM2708-Add-core-Device-Tree-support.patch
	bcm27xx/patches-5.15/950-0547-ARM-dts-Add-Pi-Zero-2-support.patch
	bcm4908/patches-5.15/033-v6.0-0001-arm64-dts-Add-DTS-files-for-bcmbca-SoC-BCM63158.patchgit
	bcm4908/patches-5.15/033-v6.0-0002-arm64-dts-Add-DTS-files-for-bcmbca-SoC-BCM4912.patchgit
	bcm4908/patches-5.15/030-v5.16-0001-arm64-dts-broadcom-bcm4908-Fix-NAND-node-name.patch
	bcm4908/patches-5.15/032-v5.18-0002-arm64-dts-broadcom-bcm4908-add-pinctrl-binding.patch
	bcm4908/patches-5.15/032-v5.18-0003-arm64-dts-broadcom-bcm4908-add-watchdog-block.patch
	bcm4908/patches-5.15/032-v5.18-0004-arm64-dts-broadcom-bcm4908-add-I2C-block.patch
	bcm4908/patches-5.15/033-v6.0-0003-ARM64-dts-Add-DTS-files-for-bcmbca-SoC-BCM6858.patchgit
	bcm4908/patches-5.15/033-v6.0-0008-arm64-dts-broadcom-bcm4908-Fix-timer-node-for-BCM490.patchgit
	bcm4908/patches-5.15/034-v6.1-0001-arm64-dts-broadcom-bcm4908-add-remaining-LED-pins.patch
	bcm4908/patches-5.15/034-v6.1-0002-arm64-dts-broadcom-bcm4908-add-LEDs-controller-block.patch
	bcm4908/patches-5.15/034-v6.1-0003-arm64-dts-broadcom-bcm4908-add-Asus-GT-AC5300-LEDs.patch
	bcm4908/patches-5.15/034-v6.1-0004-arm64-dts-bcmbca-update-BCM4908-board-dts-files.patch

All other patches automatically rebased.

Build system: x86_64
Build-tested: bcm2711/RPi4B, ramips/tplink_archer-a6-v3, filogic/xiaomi_redmi-router-ax6000-ubootmod
Run-tested: bcm2711/RPi4B, ramips/tplink_archer-a6-v3, filogic/xiaomi_redmi-router-ax6000-ubootmod

01. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v5.15.111&id=77112d23a671697f0f70695ab901f807e15d2093
02. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v5.15.111&id=fe07b3b5af01f42b291f5da0da09d047f50b33a6
03. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v5.15.111&id=273be36e420924237f6c9d43cdad96718c13dd52
04. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v5.15.111&id=fe8ab85ed4958e58e991bba0aa0a655b552b0273
05. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v5.15.111&id=6ae67829fa5e9e71f458f69db42f0e216225616a
06. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v5.15.111&id=1994284cb9226b65ca3a6744ce3320218b584f26
07. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v5.15.111&id=a46878476c5549a4fde15a31922ce80a50b23492
08. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v5.15.111&id=112ff0f2530549d50510f116474924f9c4fad590
09. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v5.15.111&id=7c253e98685e6d884d12e2618ef4d2ad90b4fbd7
10. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v5.15.111&id=8444b46e163aa9559a0af0381a1d230ec4146eb2
11. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v5.15.111&id=6d1af517817a760d7af3dee0fc4603645485495c
12. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v5.15.111&id=cc4f0e168a5630ad0491ac5328f1a89f3cf3d04e

Signed-off-by: John Audia <therealgraysky@proton.me>
2023-05-13 22:38:35 +02:00

221 lines
6.8 KiB
Diff

From a7d96ca20847ade9f29cff4521f43b8ae968b3df Mon Sep 17 00:00:00 2001
From: Selvam Sathappan Periakaruppan <quic_speriaka@quicinc.com>
Date: Tue, 21 Jun 2022 11:54:54 +0300
Subject: [PATCH] PCI: qcom: Add IPQ60xx support
IPQ60xx series of SoCs have one port of PCIe gen 3. Add support for that
platform.
The code is based on downstream[1] Codeaurora kernel v5.4 (branch
win.linuxopenwrt.2.0).
Split out the DBI registers access part from .init into .post_init. DBI
registers are only accessible after phy_power_on().
[1] https://source.codeaurora.org/quic/qsdk/oss/kernel/linux-ipq-5.4/
Link: https://lore.kernel.org/r/f7f848653c99abbf9a0f877949a44e52329543ae.1655799816.git.baruch@tkos.co.il
Tested-by: Robert Marko <robert.marko@sartura.hr>
Signed-off-by: Selvam Sathappan Periakaruppan <quic_speriaka@quicinc.com>
Signed-off-by: Baruch Siach <baruch.siach@siklu.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>
---
drivers/pci/controller/dwc/pcie-designware.h | 1 +
drivers/pci/controller/dwc/pcie-qcom.c | 130 +++++++++++++++++++
2 files changed, 131 insertions(+)
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -76,6 +76,7 @@
#define GEN3_RELATED_OFF 0x890
#define GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL BIT(0)
+#define GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS BIT(13)
#define GEN3_RELATED_OFF_GEN3_EQ_DISABLE BIT(16)
#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT 24
#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK GENMASK(25, 24)
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -52,6 +52,10 @@
#define PCIE20_PARF_DBI_BASE_ADDR 0x168
#define PCIE20_PARF_SLV_ADDR_SPACE_SIZE 0x16C
#define PCIE20_PARF_MHI_CLOCK_RESET_CTRL 0x174
+#define AHB_CLK_EN BIT(0)
+#define MSTR_AXI_CLK_EN BIT(1)
+#define BYPASS BIT(4)
+
#define PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT 0x178
#define PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2 0x1A8
#define PCIE20_PARF_LTSSM 0x1B0
@@ -181,6 +185,11 @@ struct qcom_pcie_resources_2_7_0 {
struct clk *pipe_clk;
};
+struct qcom_pcie_resources_2_9_0 {
+ struct clk_bulk_data clks[5];
+ struct reset_control *rst;
+};
+
union qcom_pcie_resources {
struct qcom_pcie_resources_1_0_0 v1_0_0;
struct qcom_pcie_resources_2_1_0 v2_1_0;
@@ -188,6 +197,7 @@ union qcom_pcie_resources {
struct qcom_pcie_resources_2_3_3 v2_3_3;
struct qcom_pcie_resources_2_4_0 v2_4_0;
struct qcom_pcie_resources_2_7_0 v2_7_0;
+ struct qcom_pcie_resources_2_9_0 v2_9_0;
};
struct qcom_pcie;
@@ -1280,6 +1290,112 @@ static void qcom_pcie_post_deinit_2_7_0(
clk_disable_unprepare(res->pipe_clk);
}
+static int qcom_pcie_get_resources_2_9_0(struct qcom_pcie *pcie)
+{
+ struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0;
+ struct dw_pcie *pci = pcie->pci;
+ struct device *dev = pci->dev;
+ int ret;
+
+ res->clks[0].id = "iface";
+ res->clks[1].id = "axi_m";
+ res->clks[2].id = "axi_s";
+ res->clks[3].id = "axi_bridge";
+ res->clks[4].id = "rchng";
+
+ ret = devm_clk_bulk_get(dev, ARRAY_SIZE(res->clks), res->clks);
+ if (ret < 0)
+ return ret;
+
+ res->rst = devm_reset_control_array_get_exclusive(dev);
+ if (IS_ERR(res->rst))
+ return PTR_ERR(res->rst);
+
+ return 0;
+}
+
+static void qcom_pcie_deinit_2_9_0(struct qcom_pcie *pcie)
+{
+ struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0;
+
+ clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks);
+}
+
+static int qcom_pcie_init_2_9_0(struct qcom_pcie *pcie)
+{
+ struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0;
+ struct device *dev = pcie->pci->dev;
+ int ret;
+
+ ret = reset_control_assert(res->rst);
+ if (ret) {
+ dev_err(dev, "reset assert failed (%d)\n", ret);
+ return ret;
+ }
+
+ /*
+ * Delay periods before and after reset deassert are working values
+ * from downstream Codeaurora kernel
+ */
+ usleep_range(2000, 2500);
+
+ ret = reset_control_deassert(res->rst);
+ if (ret) {
+ dev_err(dev, "reset deassert failed (%d)\n", ret);
+ return ret;
+ }
+
+ usleep_range(2000, 2500);
+
+ return clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks);
+}
+
+static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie)
+{
+ struct dw_pcie *pci = pcie->pci;
+ u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
+ u32 val;
+ int i;
+
+ writel(SLV_ADDR_SPACE_SZ,
+ pcie->parf + PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE);
+
+ val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
+ val &= ~BIT(0);
+ writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
+
+ writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);
+
+ writel(DEVICE_TYPE_RC, pcie->parf + PCIE20_PARF_DEVICE_TYPE);
+ writel(BYPASS | MSTR_AXI_CLK_EN | AHB_CLK_EN,
+ pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
+ writel(GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS |
+ GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL,
+ pci->dbi_base + GEN3_RELATED_OFF);
+
+ writel(MST_WAKEUP_EN | SLV_WAKEUP_EN | MSTR_ACLK_CGC_DIS |
+ SLV_ACLK_CGC_DIS | CORE_CLK_CGC_DIS |
+ AUX_PWR_DET | L23_CLK_RMV_DIS | L1_CLK_RMV_DIS,
+ pcie->parf + PCIE20_PARF_SYS_CTRL);
+
+ writel(0, pcie->parf + PCIE20_PARF_Q2A_FLUSH);
+
+ dw_pcie_dbi_ro_wr_en(pci);
+ writel(PCIE_CAP_SLOT_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP);
+
+ val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP);
+ val &= ~PCI_EXP_LNKCAP_ASPMS;
+ writel(val, pci->dbi_base + offset + PCI_EXP_LNKCAP);
+
+ writel(PCI_EXP_DEVCTL2_COMP_TMOUT_DIS, pci->dbi_base + offset +
+ PCI_EXP_DEVCTL2);
+
+ for (i = 0; i < 256; i++)
+ writel(0, pcie->parf + PCIE20_PARF_BDF_TO_SID_TABLE_N + (4 * i));
+
+ return 0;
+}
+
static int qcom_pcie_link_up(struct dw_pcie *pci)
{
u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
@@ -1471,6 +1587,15 @@ static const struct qcom_pcie_ops ops_1_
.config_sid = qcom_pcie_config_sid_sm8250,
};
+/* Qcom IP rev.: 2.9.0 Synopsys IP rev.: 5.00a */
+static const struct qcom_pcie_ops ops_2_9_0 = {
+ .get_resources = qcom_pcie_get_resources_2_9_0,
+ .init = qcom_pcie_init_2_9_0,
+ .post_init = qcom_pcie_post_init_2_9_0,
+ .deinit = qcom_pcie_deinit_2_9_0,
+ .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
+};
+
static const struct qcom_pcie_cfg apq8084_cfg = {
.ops = &ops_1_0_0,
};
@@ -1503,6 +1628,10 @@ static const struct qcom_pcie_cfg sc7280
.ops = &ops_1_9_0,
};
+static const struct qcom_pcie_cfg ipq6018_cfg = {
+ .ops = &ops_2_9_0,
+};
+
static const struct dw_pcie_ops dw_pcie_ops = {
.link_up = qcom_pcie_link_up,
.start_link = qcom_pcie_start_link,
@@ -1609,6 +1738,7 @@ static const struct of_device_id qcom_pc
{ .compatible = "qcom,pcie-sdm845", .data = &sdm845_cfg },
{ .compatible = "qcom,pcie-sm8250", .data = &sm8250_cfg },
{ .compatible = "qcom,pcie-sc7280", .data = &sc7280_cfg },
+ { .compatible = "qcom,pcie-ipq6018", .data = &ipq6018_cfg },
{ }
};