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173 lines
5.6 KiB
Diff
173 lines
5.6 KiB
Diff
From c08886564938df6796a7d98495cf5cc3f7a09337 Mon Sep 17 00:00:00 2001
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From: Eric Anholt <eric@anholt.net>
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Date: Wed, 18 Jan 2017 07:31:55 +1100
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Subject: [PATCH] clk: bcm2835: Don't rate change PLLs on behalf of DSI PLL
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dividers (v2).
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Our core PLLs are intended to be configured once and left alone. With
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the SET_RATE_PARENT, asking to set the PLLD_DSI1 clock rate would
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change PLLD just to get closer to the requested DSI clock, thus
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changing PLLD_PER, the UART and ethernet PHY clock rates downstream of
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it, and breaking ethernet.
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We *do* want PLLH to change so that PLLH_AUX can be exactly the value
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we want, though. Thus, we need to have a per-divider policy of
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whether to pass rate changes up.
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Signed-off-by: Eric Anholt <eric@anholt.net>
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Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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(cherry picked from commit 55486091bd1e1c5ed28c43c0d6b3392468a9adb5)
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---
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drivers/clk/bcm/clk-bcm2835.c | 42 ++++++++++++++++++++++++++++--------------
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1 file changed, 28 insertions(+), 14 deletions(-)
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--- a/drivers/clk/bcm/clk-bcm2835.c
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+++ b/drivers/clk/bcm/clk-bcm2835.c
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@@ -449,6 +449,7 @@ struct bcm2835_pll_divider_data {
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u32 load_mask;
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u32 hold_mask;
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u32 fixed_divider;
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+ u32 flags;
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};
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struct bcm2835_clock_data {
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@@ -1286,7 +1287,7 @@ bcm2835_register_pll_divider(struct bcm2
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init.num_parents = 1;
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init.name = divider_name;
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init.ops = &bcm2835_pll_divider_clk_ops;
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- init.flags = CLK_IGNORE_UNUSED;
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+ init.flags = data->flags | CLK_IGNORE_UNUSED;
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divider = devm_kzalloc(cprman->dev, sizeof(*divider), GFP_KERNEL);
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if (!divider)
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@@ -1525,7 +1526,8 @@ static const struct bcm2835_clk_desc clk
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.a2w_reg = A2W_PLLA_CORE,
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.load_mask = CM_PLLA_LOADCORE,
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.hold_mask = CM_PLLA_HOLDCORE,
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- .fixed_divider = 1),
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+ .fixed_divider = 1,
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+ .flags = CLK_SET_RATE_PARENT),
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[BCM2835_PLLA_PER] = REGISTER_PLL_DIV(
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.name = "plla_per",
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.source_pll = "plla",
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@@ -1533,7 +1535,8 @@ static const struct bcm2835_clk_desc clk
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.a2w_reg = A2W_PLLA_PER,
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.load_mask = CM_PLLA_LOADPER,
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.hold_mask = CM_PLLA_HOLDPER,
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- .fixed_divider = 1),
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+ .fixed_divider = 1,
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+ .flags = CLK_SET_RATE_PARENT),
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[BCM2835_PLLA_DSI0] = REGISTER_PLL_DIV(
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.name = "plla_dsi0",
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.source_pll = "plla",
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@@ -1549,7 +1552,8 @@ static const struct bcm2835_clk_desc clk
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.a2w_reg = A2W_PLLA_CCP2,
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.load_mask = CM_PLLA_LOADCCP2,
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.hold_mask = CM_PLLA_HOLDCCP2,
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- .fixed_divider = 1),
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+ .fixed_divider = 1,
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+ .flags = CLK_SET_RATE_PARENT),
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/* PLLB is used for the ARM's clock. */
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[BCM2835_PLLB] = REGISTER_PLL(
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@@ -1573,7 +1577,8 @@ static const struct bcm2835_clk_desc clk
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.a2w_reg = A2W_PLLB_ARM,
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.load_mask = CM_PLLB_LOADARM,
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.hold_mask = CM_PLLB_HOLDARM,
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- .fixed_divider = 1),
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+ .fixed_divider = 1,
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+ .flags = CLK_SET_RATE_PARENT),
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/*
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* PLLC is the core PLL, used to drive the core VPU clock.
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@@ -1602,7 +1607,8 @@ static const struct bcm2835_clk_desc clk
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.a2w_reg = A2W_PLLC_CORE0,
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.load_mask = CM_PLLC_LOADCORE0,
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.hold_mask = CM_PLLC_HOLDCORE0,
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- .fixed_divider = 1),
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+ .fixed_divider = 1,
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+ .flags = CLK_SET_RATE_PARENT),
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[BCM2835_PLLC_CORE1] = REGISTER_PLL_DIV(
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.name = "pllc_core1",
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.source_pll = "pllc",
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@@ -1610,7 +1616,8 @@ static const struct bcm2835_clk_desc clk
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.a2w_reg = A2W_PLLC_CORE1,
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.load_mask = CM_PLLC_LOADCORE1,
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.hold_mask = CM_PLLC_HOLDCORE1,
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- .fixed_divider = 1),
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+ .fixed_divider = 1,
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+ .flags = CLK_SET_RATE_PARENT),
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[BCM2835_PLLC_CORE2] = REGISTER_PLL_DIV(
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.name = "pllc_core2",
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.source_pll = "pllc",
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@@ -1618,7 +1625,8 @@ static const struct bcm2835_clk_desc clk
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.a2w_reg = A2W_PLLC_CORE2,
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.load_mask = CM_PLLC_LOADCORE2,
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.hold_mask = CM_PLLC_HOLDCORE2,
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- .fixed_divider = 1),
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+ .fixed_divider = 1,
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+ .flags = CLK_SET_RATE_PARENT),
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[BCM2835_PLLC_PER] = REGISTER_PLL_DIV(
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.name = "pllc_per",
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.source_pll = "pllc",
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@@ -1626,7 +1634,8 @@ static const struct bcm2835_clk_desc clk
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.a2w_reg = A2W_PLLC_PER,
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.load_mask = CM_PLLC_LOADPER,
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.hold_mask = CM_PLLC_HOLDPER,
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- .fixed_divider = 1),
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+ .fixed_divider = 1,
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+ .flags = CLK_SET_RATE_PARENT),
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/*
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* PLLD is the display PLL, used to drive DSI display panels.
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@@ -1655,7 +1664,8 @@ static const struct bcm2835_clk_desc clk
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.a2w_reg = A2W_PLLD_CORE,
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.load_mask = CM_PLLD_LOADCORE,
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.hold_mask = CM_PLLD_HOLDCORE,
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- .fixed_divider = 1),
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+ .fixed_divider = 1,
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+ .flags = CLK_SET_RATE_PARENT),
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[BCM2835_PLLD_PER] = REGISTER_PLL_DIV(
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.name = "plld_per",
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.source_pll = "plld",
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@@ -1663,7 +1673,8 @@ static const struct bcm2835_clk_desc clk
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.a2w_reg = A2W_PLLD_PER,
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.load_mask = CM_PLLD_LOADPER,
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.hold_mask = CM_PLLD_HOLDPER,
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- .fixed_divider = 1),
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+ .fixed_divider = 1,
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+ .flags = CLK_SET_RATE_PARENT),
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[BCM2835_PLLD_DSI0] = REGISTER_PLL_DIV(
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.name = "plld_dsi0",
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.source_pll = "plld",
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@@ -1708,7 +1719,8 @@ static const struct bcm2835_clk_desc clk
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.a2w_reg = A2W_PLLH_RCAL,
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.load_mask = CM_PLLH_LOADRCAL,
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.hold_mask = 0,
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- .fixed_divider = 10),
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+ .fixed_divider = 10,
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+ .flags = CLK_SET_RATE_PARENT),
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[BCM2835_PLLH_AUX] = REGISTER_PLL_DIV(
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.name = "pllh_aux",
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.source_pll = "pllh",
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@@ -1716,7 +1728,8 @@ static const struct bcm2835_clk_desc clk
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.a2w_reg = A2W_PLLH_AUX,
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.load_mask = CM_PLLH_LOADAUX,
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.hold_mask = 0,
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- .fixed_divider = 1),
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+ .fixed_divider = 1,
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+ .flags = CLK_SET_RATE_PARENT),
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[BCM2835_PLLH_PIX] = REGISTER_PLL_DIV(
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.name = "pllh_pix",
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.source_pll = "pllh",
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@@ -1724,7 +1737,8 @@ static const struct bcm2835_clk_desc clk
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.a2w_reg = A2W_PLLH_PIX,
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.load_mask = CM_PLLH_LOADPIX,
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.hold_mask = 0,
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- .fixed_divider = 10),
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+ .fixed_divider = 10,
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+ .flags = CLK_SET_RATE_PARENT),
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/* the clocks */
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