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103 lines
3.4 KiB
Diff
103 lines
3.4 KiB
Diff
From 147a46beeb49c6baabb85126d570f330a2ba7cad Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
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Date: Sat, 14 Sep 2013 20:48:40 -0300
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Subject: [PATCH] clk: sunxi: Implement muxable AHB clock
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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sun5i and sun7i have a mux to change the AHB clock parent, this commit
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adds support for it on the driver.
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Signed-off-by: Emilio López <emilio@elopez.com.ar>
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---
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Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
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drivers/clk/sunxi/clk-sunxi.c | 37 +++++++++++++++++++++++
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2 files changed, 38 insertions(+)
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diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
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index e840cb2..941bd93 100644
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--- a/Documentation/devicetree/bindings/clock/sunxi.txt
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+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
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@@ -15,6 +15,7 @@ Required properties:
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"allwinner,sun4i-axi-clk" - for the AXI clock
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"allwinner,sun4i-axi-gates-clk" - for the AXI gates
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"allwinner,sun4i-ahb-clk" - for the AHB clock
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+ "allwinner,sun5i-a13-ahb-clk" - for the AHB clock on A13
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"allwinner,sun4i-ahb-gates-clk" - for the AHB gates on A10
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"allwinner,sun5i-a13-ahb-gates-clk" - for the AHB gates on A13
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"allwinner,sun5i-a10s-ahb-gates-clk" - for the AHB gates on A10s
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diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
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index 0ecaa18..360d705 100644
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--- a/drivers/clk/sunxi/clk-sunxi.c
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+++ b/drivers/clk/sunxi/clk-sunxi.c
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@@ -240,7 +240,32 @@ static void sun4i_get_pll5_factors(u32 *freq, u32 parent_rate,
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*n = DIV_ROUND_UP(div, (*k+1));
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}
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+/**
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+ * sun5i_get_ahb_factors() - calculates p factor for AHB
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+ * AHB rate is calculated as follows
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+ * rate = parent_rate >> p
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+ */
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+static void sun5i_a13_get_ahb_factors(u32 *freq, u32 parent_rate,
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+ u8 *n, u8 *k, u8 *m, u8 *p)
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+{
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+ u8 div;
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+
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+ /* This clock can only divide, so we will never achieve a higher
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+ * rate than the parent's */
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+ if (*freq > parent_rate)
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+ *freq = parent_rate;
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+
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+ /* Normalize value to a parent multiple */
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+ div = *freq / parent_rate;
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+ *freq = parent_rate * div;
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+
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+ /* we were called to round the frequency, we can now return */
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+ if (n == NULL)
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+ return;
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+
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+ *p = div;
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+}
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/**
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* sun4i_get_apb1_factors() - calculates m, p factors for APB1
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@@ -366,6 +391,11 @@ struct factors_data {
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.kwidth = 2,
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};
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+static struct clk_factors_config sun5i_a13_ahb_config = {
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+ .pshift = 4,
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+ .pwidth = 2,
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+};
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+
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static struct clk_factors_config sun4i_apb1_config = {
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.mshift = 0,
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.mwidth = 5,
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@@ -399,6 +429,12 @@ struct factors_data {
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.getter = sun4i_get_pll5_factors,
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};
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+static const struct factors_data sun5i_a13_ahb_data __initconst = {
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+ .mux = 6,
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+ .table = &sun5i_a13_ahb_config,
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+ .getter = sun5i_a13_get_ahb_factors,
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+};
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+
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static const struct factors_data sun4i_apb1_data __initconst = {
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.mux = 24,
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.table = &sun4i_apb1_config,
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@@ -842,6 +878,7 @@ static void __init sunxi_divs_clk_setup(struct device_node *node,
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static const struct of_device_id clk_factors_match[] __initconst = {
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{.compatible = "allwinner,sun4i-pll1-clk", .data = &sun4i_pll1_data,},
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{.compatible = "allwinner,sun6i-a31-pll1-clk", .data = &sun6i_a31_pll1_data,},
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+ {.compatible = "allwinner,sun5i-a13-ahb-clk", .data = &sun5i_a13_ahb_data,},
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{.compatible = "allwinner,sun4i-apb1-clk", .data = &sun4i_apb1_data,},
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{.compatible = "allwinner,sun4i-mod0-clk", .data = &sun4i_mod0_data,},
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{}
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--
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1.8.5.1
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