mirror of
https://github.com/openwrt/openwrt.git
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199 lines
5.2 KiB
Diff
199 lines
5.2 KiB
Diff
From 0ae543fe8ae8b9ea7166c39b00e977506eccdf4b Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
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Date: Wed, 4 Sep 2013 21:21:16 -0300
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Subject: [PATCH] ARM: sun5i: dt: mod0 clocks
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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This commit adds all the mod0 clocks available on A10 and A13. The list
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has been constructed by looking at the Allwinner code release for A10S
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and A13.
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Signed-off-by: Emilio López <emilio@elopez.com.ar>
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Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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---
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arch/arm/boot/dts/sun5i-a10s.dtsi | 77 +++++++++++++++++++++++++++++++++++++++
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arch/arm/boot/dts/sun5i-a13.dtsi | 77 +++++++++++++++++++++++++++++++++++++++
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2 files changed, 154 insertions(+)
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diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
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index 86e06e4..82b5ce6 100644
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--- a/arch/arm/boot/dts/sun5i-a10s.dtsi
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+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
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@@ -173,6 +173,83 @@
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"apb1_i2c2", "apb1_uart0", "apb1_uart1",
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"apb1_uart2", "apb1_uart3";
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};
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+
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+ nand: nand@01c20080 {
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+ #clock-cells = <0>;
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+ compatible = "allwinner,sun4i-mod0-clk";
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+ reg = <0x01c20080 0x4>;
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+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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+ };
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+
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+ ms: ms@01c20084 {
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+ #clock-cells = <0>;
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+ compatible = "allwinner,sun4i-mod0-clk";
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+ reg = <0x01c20084 0x4>;
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+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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+ };
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+
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+ mmc0: mmc0@01c20088 {
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+ #clock-cells = <0>;
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+ compatible = "allwinner,sun4i-mod0-clk";
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+ reg = <0x01c20088 0x4>;
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+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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+ };
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+
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+ mmc1: mmc1@01c2008c {
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+ #clock-cells = <0>;
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+ compatible = "allwinner,sun4i-mod0-clk";
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+ reg = <0x01c2008c 0x4>;
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+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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+ };
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+
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+ mmc2: mmc2@01c20090 {
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+ #clock-cells = <0>;
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+ compatible = "allwinner,sun4i-mod0-clk";
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+ reg = <0x01c20090 0x4>;
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+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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+ };
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+
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+ ts: ts@01c20098 {
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+ #clock-cells = <0>;
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+ compatible = "allwinner,sun4i-mod0-clk";
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+ reg = <0x01c20098 0x4>;
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+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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+ };
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+
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+ ss: ss@01c2009c {
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+ #clock-cells = <0>;
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+ compatible = "allwinner,sun4i-mod0-clk";
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+ reg = <0x01c2009c 0x4>;
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+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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+ };
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+
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+ spi0: spi0@01c200a0 {
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+ #clock-cells = <0>;
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+ compatible = "allwinner,sun4i-mod0-clk";
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+ reg = <0x01c200a0 0x4>;
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+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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+ };
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+
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+ spi1: spi1@01c200a4 {
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+ #clock-cells = <0>;
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+ compatible = "allwinner,sun4i-mod0-clk";
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+ reg = <0x01c200a4 0x4>;
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+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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+ };
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+
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+ spi2: spi2@01c200a8 {
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+ #clock-cells = <0>;
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+ compatible = "allwinner,sun4i-mod0-clk";
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+ reg = <0x01c200a8 0x4>;
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+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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+ };
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+
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+ ir0: ir0@01c200b0 {
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+ #clock-cells = <0>;
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+ compatible = "allwinner,sun4i-mod0-clk";
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+ reg = <0x01c200b0 0x4>;
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+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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+ };
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};
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soc@01c00000 {
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diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
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index cded3c7..938e6d3 100644
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--- a/arch/arm/boot/dts/sun5i-a13.dtsi
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+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
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@@ -170,6 +170,83 @@
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clock-output-names = "apb1_i2c0", "apb1_i2c1",
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"apb1_i2c2", "apb1_uart1", "apb1_uart3";
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};
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+
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+ nand: nand@01c20080 {
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+ #clock-cells = <0>;
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+ compatible = "allwinner,sun4i-mod0-clk";
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+ reg = <0x01c20080 0x4>;
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+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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+ };
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+
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+ ms: ms@01c20084 {
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+ #clock-cells = <0>;
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+ compatible = "allwinner,sun4i-mod0-clk";
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+ reg = <0x01c20084 0x4>;
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+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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+ };
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+
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+ mmc0: mmc0@01c20088 {
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+ #clock-cells = <0>;
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+ compatible = "allwinner,sun4i-mod0-clk";
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+ reg = <0x01c20088 0x4>;
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+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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+ };
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+
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+ mmc1: mmc1@01c2008c {
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+ #clock-cells = <0>;
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+ compatible = "allwinner,sun4i-mod0-clk";
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+ reg = <0x01c2008c 0x4>;
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+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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+ };
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+
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+ mmc2: mmc2@01c20090 {
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+ #clock-cells = <0>;
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+ compatible = "allwinner,sun4i-mod0-clk";
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+ reg = <0x01c20090 0x4>;
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+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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+ };
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+
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+ ts: ts@01c20098 {
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+ #clock-cells = <0>;
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+ compatible = "allwinner,sun4i-mod0-clk";
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+ reg = <0x01c20098 0x4>;
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+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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+ };
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+
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+ ss: ss@01c2009c {
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+ #clock-cells = <0>;
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+ compatible = "allwinner,sun4i-mod0-clk";
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+ reg = <0x01c2009c 0x4>;
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+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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+ };
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+
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+ spi0: spi0@01c200a0 {
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+ #clock-cells = <0>;
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+ compatible = "allwinner,sun4i-mod0-clk";
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+ reg = <0x01c200a0 0x4>;
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+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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+ };
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+
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+ spi1: spi1@01c200a4 {
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+ #clock-cells = <0>;
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+ compatible = "allwinner,sun4i-mod0-clk";
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+ reg = <0x01c200a4 0x4>;
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+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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+ };
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+
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+ spi2: spi2@01c200a8 {
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+ #clock-cells = <0>;
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+ compatible = "allwinner,sun4i-mod0-clk";
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+ reg = <0x01c200a8 0x4>;
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+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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+ };
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+
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+ ir0: ir0@01c200b0 {
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+ #clock-cells = <0>;
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+ compatible = "allwinner,sun4i-mod0-clk";
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+ reg = <0x01c200b0 0x4>;
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+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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+ };
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};
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soc@01c00000 {
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--
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1.8.5.1
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