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310 lines
8.8 KiB
Diff
310 lines
8.8 KiB
Diff
From cad227619badf2a0ff2593d9935fedc84d5ef1ef Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
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Date: Sun, 26 May 2013 14:23:50 -0300
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Subject: [PATCH] clk: sunxi: add PLL5 and PLL6 support
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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This commit implements PLL5 and PLL6 support on the sunxi clock driver.
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These PLLs use a similar factor clock, but differ on their outputs.
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Signed-off-by: Emilio López <emilio@elopez.com.ar>
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---
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Documentation/devicetree/bindings/clock/sunxi.txt | 2 +
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drivers/clk/sunxi/clk-sunxi.c | 182 +++++++++++++++++++++-
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2 files changed, 177 insertions(+), 7 deletions(-)
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diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
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index 7d9245f..773f3ae 100644
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--- a/Documentation/devicetree/bindings/clock/sunxi.txt
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+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
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@@ -9,6 +9,8 @@ Required properties:
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"allwinner,sun4i-osc-clk" - for a gatable oscillator
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"allwinner,sun4i-pll1-clk" - for the main PLL clock and PLL4
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"allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31
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+ "allwinner,sun4i-pll5-clk" - for the PLL5 clock
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+ "allwinner,sun4i-pll6-clk" - for the PLL6 clock
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"allwinner,sun4i-cpu-clk" - for the CPU multiplexer clock
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"allwinner,sun4i-axi-clk" - for the AXI clock
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"allwinner,sun4i-axi-gates-clk" - for the AXI gates
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diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
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index c0b0675..6947ba9 100644
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--- a/drivers/clk/sunxi/clk-sunxi.c
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+++ b/drivers/clk/sunxi/clk-sunxi.c
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@@ -210,6 +210,40 @@ static void sun6i_a31_get_pll1_factors(u32 *freq, u32 parent_rate,
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}
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/**
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+ * sun4i_get_pll5_factors() - calculates n, k factors for PLL5
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+ * PLL5 rate is calculated as follows
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+ * rate = parent_rate * n * (k + 1)
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+ * parent_rate is always 24Mhz
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+ */
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+
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+static void sun4i_get_pll5_factors(u32 *freq, u32 parent_rate,
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+ u8 *n, u8 *k, u8 *m, u8 *p)
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+{
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+ u8 div;
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+
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+ /* Normalize value to a 24M multiple */
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+ div = *freq / 24000000;
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+ *freq = 24000000 * div;
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+
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+ /* we were called to round the frequency, we can now return */
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+ if (n == NULL)
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+ return;
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+
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+ if (div < 31)
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+ *k = 0;
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+ else if (div / 2 < 31)
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+ *k = 1;
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+ else if (div / 3 < 31)
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+ *k = 2;
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+ else
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+ *k = 3;
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+
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+ *n = DIV_ROUND_UP(div, (*k+1));
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+}
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+
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+
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+
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+/**
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* sun4i_get_apb1_factors() - calculates m, p factors for APB1
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* APB1 rate is calculated as follows
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* rate = (parent_rate >> p) / (m + 1);
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@@ -285,6 +319,13 @@ struct factors_data {
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.mwidth = 2,
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};
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+static struct clk_factors_config sun4i_pll5_config = {
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+ .nshift = 8,
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+ .nwidth = 5,
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+ .kshift = 4,
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+ .kwidth = 2,
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+};
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+
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static struct clk_factors_config sun4i_apb1_config = {
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.mshift = 0,
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.mwidth = 5,
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@@ -304,13 +345,19 @@ struct factors_data {
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.getter = sun6i_a31_get_pll1_factors,
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};
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+static const struct factors_data sun4i_pll5_data __initconst = {
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+ .enable = 31,
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+ .table = &sun4i_pll5_config,
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+ .getter = sun4i_get_pll5_factors,
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+};
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+
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static const struct factors_data sun4i_apb1_data __initconst = {
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.table = &sun4i_apb1_config,
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.getter = sun4i_get_apb1_factors,
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};
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-static void __init sunxi_factors_clk_setup(struct device_node *node,
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- struct factors_data *data)
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+static struct clk * __init sunxi_factors_clk_setup(struct device_node *node,
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+ const struct factors_data *data)
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{
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struct clk *clk;
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struct clk_factors *factors;
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@@ -321,6 +368,7 @@ static void __init sunxi_factors_clk_setup(struct device_node *node,
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const char *clk_name = node->name;
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const char *parents[5];
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void *reg;
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+ unsigned long flags;
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int i = 0;
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reg = of_iomap(node, 0);
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@@ -331,14 +379,14 @@ static void __init sunxi_factors_clk_setup(struct device_node *node,
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factors = kzalloc(sizeof(struct clk_factors), GFP_KERNEL);
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if (!factors)
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- return;
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+ return NULL;
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/* Add a gate if this factor clock can be gated */
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if (data->enable) {
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gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL);
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if (!gate) {
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kfree(factors);
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- return;
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+ return NULL;
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}
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/* set up gate properties */
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@@ -354,7 +402,7 @@ static void __init sunxi_factors_clk_setup(struct device_node *node,
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if (!mux) {
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kfree(factors);
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kfree(gate);
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- return;
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+ return NULL;
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}
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/* set up gate properties */
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@@ -371,17 +419,21 @@ static void __init sunxi_factors_clk_setup(struct device_node *node,
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factors->get_factors = data->getter;
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factors->lock = &clk_lock;
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+ /* We should not disable pll5, it powers the RAM */
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+ flags = !strcmp("pll5", clk_name) ? CLK_IGNORE_UNUSED : 0;
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+
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clk = clk_register_composite(NULL, clk_name,
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parents, i,
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mux_hw, &clk_mux_ops,
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&factors->hw, &clk_factors_ops,
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- gate_hw, &clk_gate_ops,
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- i ? 0 : CLK_IS_ROOT);
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+ gate_hw, &clk_gate_ops, flags);
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if (!IS_ERR(clk)) {
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of_clk_add_provider(node, of_clk_src_simple_get, clk);
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clk_register_clkdev(clk, clk_name, NULL);
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}
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+
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+ return clk;
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}
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@@ -616,6 +668,112 @@ static void __init sunxi_gates_clk_setup(struct device_node *node,
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of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
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}
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+
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+
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+/**
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+ * sunxi_divs_clk_setup() - Setup function for leaf divisors on clocks
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+ */
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+
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+#define SUNXI_DIVS_MAX_QTY 2
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+#define SUNXI_DIVISOR_WIDTH 2
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+
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+struct divs_data {
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+ const struct factors_data *factors; /* data for the factor clock */
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+ struct {
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+ u8 fixed; /* is it a fixed divisor? if not... */
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+ struct clk_div_table *table; /* is it a table based divisor? */
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+ u8 shift; /* otherwise it's a normal divisor with this shift */
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+ u8 pow; /* is it power-of-two based? */
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+ } div[SUNXI_DIVS_MAX_QTY];
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+};
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+
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+static struct clk_div_table pll6_sata_table[] = {
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+ { .val = 0, .div = 6, },
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+ { .val = 1, .div = 12, },
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+ { .val = 2, .div = 18, },
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+ { .val = 3, .div = 24, },
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+ { } /* sentinel */
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+};
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+
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+static const struct divs_data pll5_divs_data __initconst = {
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+ .factors = &sun4i_pll5_data,
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+ .div = {
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+ { .shift = 0, .pow = 0, }, /* M, DDR */
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+ { .shift = 16, .pow = 1, }, /* P, other */
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+ }
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+};
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+
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+static const struct divs_data pll6_divs_data __initconst = {
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+ .factors = &sun4i_pll5_data,
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+ .div = {
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+ { .shift = 0, .table = pll6_sata_table }, /* M, SATA */
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+ { .fixed = 2 }, /* P, other */
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+ }
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+};
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+
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+static void __init sunxi_divs_clk_setup(struct device_node *node,
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+ struct divs_data *data)
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+{
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+ struct clk_onecell_data *clk_data;
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+ const char *parent = node->name;
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+ const char *clk_name;
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+ struct clk **clks, *pclk;
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+ void *reg;
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+ int i = 0;
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+ int flags, clkflags;
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+
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+ /* Set up factor clock that we will be dividing */
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+ pclk = sunxi_factors_clk_setup(node, data->factors);
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+
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+ reg = of_iomap(node, 0);
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+
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+ clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
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+ if (!clk_data)
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+ return;
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+ clks = kzalloc(SUNXI_DIVS_MAX_QTY * sizeof(struct clk *), GFP_KERNEL);
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+ if (!clks) {
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+ kfree(clk_data);
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+ return;
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+ }
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+ clk_data->clks = clks;
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+
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+ /* It's not a good idea to have automatic reparenting changing
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+ * our RAM clock! */
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+ clkflags = !strcmp("pll5", parent) ? 0 : CLK_SET_RATE_PARENT;
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+
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+ for (i = 0; i < SUNXI_DIVS_MAX_QTY; i++) {
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+ if (of_property_read_string_index(node, "clock-output-names",
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+ i, &clk_name) != 0)
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+ break;
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+
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+ if (data->div[i].fixed) {
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+ clks[i] = clk_register_fixed_factor(NULL, clk_name,
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+ parent, clkflags,
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+ 1, data->div[i].fixed);
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+ } else {
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+ flags = data->div[i].pow ? CLK_DIVIDER_POWER_OF_TWO : 0;
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+ clks[i] = clk_register_divider_table(NULL, clk_name,
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+ parent, clkflags, reg,
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+ data->div[i].shift,
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+ SUNXI_DIVISOR_WIDTH, flags,
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+ data->div[i].table, &clk_lock);
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+ }
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+
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+ WARN_ON(IS_ERR(clk_data->clks[i]));
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+ clk_register_clkdev(clks[i], clk_name, NULL);
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+ }
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+
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+ /* The last clock available on the getter is the parent */
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+ clks[i++] = pclk;
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+
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+ /* Adjust to the real max */
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+ clk_data->clk_num = i;
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+
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+ of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
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+}
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+
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+
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+
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/* Matches for factors clocks */
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static const struct of_device_id clk_factors_match[] __initconst = {
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{.compatible = "allwinner,sun4i-pll1-clk", .data = &sun4i_pll1_data,},
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@@ -633,6 +791,13 @@ static void __init sunxi_gates_clk_setup(struct device_node *node,
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{}
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};
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+/* Matches for divided outputs */
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+static const struct of_device_id clk_divs_match[] __initconst = {
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+ {.compatible = "allwinner,sun4i-pll5-clk", .data = &pll5_divs_data,},
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+ {.compatible = "allwinner,sun4i-pll6-clk", .data = &pll6_divs_data,},
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+ {}
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+};
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+
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/* Matches for mux clocks */
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static const struct of_device_id clk_mux_match[] __initconst = {
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{.compatible = "allwinner,sun4i-cpu-clk", .data = &sun4i_cpu_mux_data,},
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@@ -688,6 +853,9 @@ void __init sunxi_init_clocks(void)
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/* Register divider clocks */
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of_sunxi_table_clock_setup(clk_div_match, sunxi_divider_clk_setup);
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+ /* Register divided output clocks */
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+ of_sunxi_table_clock_setup(clk_divs_match, sunxi_divs_clk_setup);
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+
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/* Register mux clocks */
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of_sunxi_table_clock_setup(clk_mux_match, sunxi_mux_clk_setup);
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--
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1.8.4
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