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60 lines
2.3 KiB
Diff
60 lines
2.3 KiB
Diff
From b67cad33176e472df6d16a24ee7624299bdcd5d5 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
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Date: Fri, 16 Jun 2023 12:58:27 +0200
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Subject: [PATCH] ARM: dts: BCM5301X: Add cells sizes to PCIe nodes
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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This fixes:
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arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dtb: pcie@12000: '#address-cells' is a required property
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From schema: /lib/python3.10/site-packages/dtschema/schemas/pci/pci-bus.yaml
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arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dtb: pcie@12000: '#size-cells' is a required property
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From schema: /lib/python3.10/site-packages/dtschema/schemas/pci/pci-bus.yaml
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arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dtb: pcie@13000: '#address-cells' is a required property
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From schema: /lib/python3.10/site-packages/dtschema/schemas/pci/pci-bus.yaml
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arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dtb: pcie@13000: '#size-cells' is a required property
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From schema: /lib/python3.10/site-packages/dtschema/schemas/pci/pci-bus.yaml
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arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dtb: pcie@14000: '#address-cells' is a required property
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From schema: /lib/python3.10/site-packages/dtschema/schemas/pci/pci-bus.yaml
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arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dtb: pcie@14000: '#size-cells' is a required property
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From schema: /lib/python3.10/site-packages/dtschema/schemas/pci/pci-bus.yaml
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Two properties that need to be added later are "device_type" and
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"ranges". Adding "device_type" on its own causes a new warning and the
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value of "ranges" needs to be determined yet.
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Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
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Link: https://lore.kernel.org/r/20230616105827.21656-1-zajec5@gmail.com
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Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
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---
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arch/arm/boot/dts/bcm-ns.dtsi | 9 +++++++++
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1 file changed, 9 insertions(+)
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--- a/arch/arm/boot/dts/bcm-ns.dtsi
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+++ b/arch/arm/boot/dts/bcm-ns.dtsi
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@@ -176,14 +176,23 @@
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pcie0: pcie@12000 {
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reg = <0x00012000 0x1000>;
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+
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+ #address-cells = <3>;
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+ #size-cells = <2>;
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};
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pcie1: pcie@13000 {
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reg = <0x00013000 0x1000>;
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+
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+ #address-cells = <3>;
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+ #size-cells = <2>;
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};
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pcie2: pcie@14000 {
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reg = <0x00014000 0x1000>;
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+
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+ #address-cells = <3>;
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+ #size-cells = <2>;
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};
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usb2: usb2@21000 {
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