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f80272dd9c
Refreshed all patches. Remove upstreamed: - 302-0002-dmaengine-dw-implement-per-channel-protection-contro.patch Fixes: - CVE-2019-19332 Compile-tested on: cns3xxx Runtime-tested on: cns3xxx Signed-off-by: Koen Vandeputte <koen.vandeputte@ncentric.com>
113 lines
3.5 KiB
Diff
113 lines
3.5 KiB
Diff
From 4b5b79998af61db8b0506fba6c0f33b57ea457bd Mon Sep 17 00:00:00 2001
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From: Christian Lamparter <chunkeey@gmail.com>
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Date: Wed, 4 Oct 2017 01:00:13 +0200
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Subject: [PATCH 21/25] crypto: crypto4xx - fix stalls under heavy load
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If the crypto4xx device is continuously loaded by dm-crypt
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and ipsec work, it will start to work intermittent after a
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few (between 20-30) seconds, hurting throughput and latency.
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This patch contains various stability improvements in order
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to fix this issue. So far, the hardware has survived more
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than a day without suffering any stalls under the continuous
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load.
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Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
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Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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---
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drivers/crypto/amcc/crypto4xx_core.c | 33 ++++++++++++++++++---------------
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drivers/crypto/amcc/crypto4xx_reg_def.h | 3 +++
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2 files changed, 21 insertions(+), 15 deletions(-)
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--- a/drivers/crypto/amcc/crypto4xx_core.c
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+++ b/drivers/crypto/amcc/crypto4xx_core.c
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@@ -280,17 +280,20 @@ static u32 crypto4xx_get_pd_from_pdr_nol
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static u32 crypto4xx_put_pd_to_pdr(struct crypto4xx_device *dev, u32 idx)
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{
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struct pd_uinfo *pd_uinfo = &dev->pdr_uinfo[idx];
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+ u32 tail;
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unsigned long flags;
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spin_lock_irqsave(&dev->core_dev->lock, flags);
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+ pd_uinfo->state = PD_ENTRY_FREE;
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+
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if (dev->pdr_tail != PPC4XX_LAST_PD)
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dev->pdr_tail++;
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else
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dev->pdr_tail = 0;
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- pd_uinfo->state = PD_ENTRY_FREE;
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+ tail = dev->pdr_tail;
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spin_unlock_irqrestore(&dev->core_dev->lock, flags);
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- return 0;
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+ return tail;
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}
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/**
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@@ -859,16 +862,16 @@ int crypto4xx_build_pd(struct crypto_asy
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}
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}
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- sa->sa_command_1.bf.hash_crypto_offset = 0;
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- pd->pd_ctl.w = 0;
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- pd->pd_ctl.bf.hash_final =
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- (crypto_tfm_alg_type(req->tfm) == CRYPTO_ALG_TYPE_AHASH);
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- pd->pd_ctl.bf.host_ready = 1;
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+ pd->pd_ctl.w = PD_CTL_HOST_READY |
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+ ((crypto_tfm_alg_type(req->tfm) == CRYPTO_ALG_TYPE_AHASH) |
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+ (crypto_tfm_alg_type(req->tfm) == CRYPTO_ALG_TYPE_AEAD) ?
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+ PD_CTL_HASH_FINAL : 0);
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pd->pd_ctl_len.w = 0x00400000 | datalen;
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pd_uinfo->state = PD_ENTRY_INUSE | (is_busy ? PD_ENTRY_BUSY : 0);
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wmb();
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/* write any value to push engine to read a pd */
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+ writel(0, dev->ce_base + CRYPTO4XX_INT_DESCR_RD);
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writel(1, dev->ce_base + CRYPTO4XX_INT_DESCR_RD);
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return is_busy ? -EBUSY : -EINPROGRESS;
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}
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@@ -969,23 +972,23 @@ static void crypto4xx_bh_tasklet_cb(unsi
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struct crypto4xx_core_device *core_dev = dev_get_drvdata(dev);
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struct pd_uinfo *pd_uinfo;
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struct ce_pd *pd;
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- u32 tail;
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+ u32 tail = core_dev->dev->pdr_tail;
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+ u32 head = core_dev->dev->pdr_head;
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- while (core_dev->dev->pdr_head != core_dev->dev->pdr_tail) {
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- tail = core_dev->dev->pdr_tail;
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+ do {
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pd_uinfo = &core_dev->dev->pdr_uinfo[tail];
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pd = &core_dev->dev->pdr[tail];
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if ((pd_uinfo->state & PD_ENTRY_INUSE) &&
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- pd->pd_ctl.bf.pe_done &&
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- !pd->pd_ctl.bf.host_ready) {
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- pd->pd_ctl.bf.pe_done = 0;
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+ ((READ_ONCE(pd->pd_ctl.w) &
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+ (PD_CTL_PE_DONE | PD_CTL_HOST_READY)) ==
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+ PD_CTL_PE_DONE)) {
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crypto4xx_pd_done(core_dev->dev, tail);
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- crypto4xx_put_pd_to_pdr(core_dev->dev, tail);
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+ tail = crypto4xx_put_pd_to_pdr(core_dev->dev, tail);
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} else {
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/* if tail not done, break */
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break;
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}
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- }
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+ } while (head != tail);
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}
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/**
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--- a/drivers/crypto/amcc/crypto4xx_reg_def.h
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+++ b/drivers/crypto/amcc/crypto4xx_reg_def.h
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@@ -261,6 +261,9 @@ union ce_pd_ctl {
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} bf;
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u32 w;
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} __attribute__((packed));
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+#define PD_CTL_HASH_FINAL BIT(4)
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+#define PD_CTL_PE_DONE BIT(1)
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+#define PD_CTL_HOST_READY BIT(0)
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union ce_pd_ctl_len {
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struct {
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