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ade563ba84
Signed-off-by: Felix Fietkau <nbd@nbd.name>
70 lines
1.8 KiB
Diff
70 lines
1.8 KiB
Diff
From 21d106f15262f5a2ef7531636e0703ee61c33c61 Mon Sep 17 00:00:00 2001
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From: Sungbo Eo <mans0n@gorani.run>
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Date: Sun, 8 Aug 2021 21:38:40 +0900
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Subject: [PATCH 2/2] arm: dts: mt7623: add musb device nodes
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MT7623 has an musb controller that is compatible with the one from MT2701.
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Signed-off-by: Sungbo Eo <mans0n@gorani.run>
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---
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arch/arm/boot/dts/mt7623.dtsi | 34 ++++++++++++++++++++++++++++++++++
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arch/arm/boot/dts/mt7623a.dtsi | 4 ++++
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2 files changed, 38 insertions(+)
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--- a/arch/arm/boot/dts/mt7623.dtsi
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+++ b/arch/arm/boot/dts/mt7623.dtsi
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@@ -585,6 +585,40 @@
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status = "disabled";
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};
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+ usb0: usb@11200000 {
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+ compatible = "mediatek,mt7623-musb",
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+ "mediatek,mtk-musb";
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+ reg = <0 0x11200000 0 0x1000>;
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+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_LOW>;
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+ interrupt-names = "mc";
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+ phys = <&u2port2 PHY_TYPE_USB2>;
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+ dr_mode = "otg";
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+ clocks = <&pericfg CLK_PERI_USB0>,
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+ <&pericfg CLK_PERI_USB0_MCU>,
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+ <&pericfg CLK_PERI_USB_SLV>;
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+ clock-names = "main","mcu","univpll";
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+ power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
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+ status = "disabled";
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+ };
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+
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+ u2phy1: t-phy@11210000 {
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+ compatible = "mediatek,mt7623-tphy",
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+ "mediatek,generic-tphy-v1";
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+ reg = <0 0x11210000 0 0x0800>;
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+ #address-cells = <2>;
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+ #size-cells = <2>;
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+ ranges;
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+ status = "disabled";
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+
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+ u2port2: usb-phy@11210800 {
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+ reg = <0 0x11210800 0 0x0100>;
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+ clocks = <&topckgen CLK_TOP_USB_PHY48M>;
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+ clock-names = "ref";
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+ #phy-cells = <1>;
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+ status = "okay";
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+ };
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+ };
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+
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audsys: clock-controller@11220000 {
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compatible = "mediatek,mt7623-audsys",
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"mediatek,mt2701-audsys",
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--- a/arch/arm/boot/dts/mt7623a.dtsi
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+++ b/arch/arm/boot/dts/mt7623a.dtsi
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@@ -35,6 +35,10 @@
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clock-names = "ethif";
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};
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+&usb0 {
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+ power-domains = <&scpsys MT7623A_POWER_DOMAIN_IFR_MSC>;
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+};
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+
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&usb1 {
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power-domains = <&scpsys MT7623A_POWER_DOMAIN_HIF>;
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};
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